Merge pull request #584 from lioncash/loads

thumb32: Implement Thumb-2 Load Byte and Memory Hints instructions

include/dynarmic/A32/config.h

@@ -48,6 +48,8 @@ enum class Exception {
     PreloadData,
     /// A PLDW instruction was executed. (Hint instruction.)
     PreloadDataWithIntentToWrite,
+    /// A PLI instruction was executed. (Hint instruction.)
+    PreloadInstruction,
 };
 
 /// These function pointers may be inserted into compiled code.

src/CMakeLists.txt

@@ -160,6 +160,9 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
         frontend/A32/translate/impl/thumb32_data_processing_register.cpp
         frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp
         frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
+        frontend/A32/translate/impl/thumb32_load_byte.cpp
+        frontend/A32/translate/impl/thumb32_load_halfword.cpp
+        frontend/A32/translate/impl/thumb32_load_word.cpp
         frontend/A32/translate/impl/thumb32_long_multiply.cpp
         frontend/A32/translate/impl/thumb32_misc.cpp
         frontend/A32/translate/impl/thumb32_multiply.cpp

src/frontend/A32/decoder/thumb32.inc

@@ -146,24 +146,24 @@ INST(thumb32_STRH,           "STRH (reg)",               "111110000010nnnntttt00
 INST(thumb32_STR_reg,        "STR (reg)",                "111110000100nnnntttt000000iimmmm")
 
 // Load Byte and Memory Hints
-//INST(thumb32_PLD_lit,        "PLD (lit)",                "11111000-00111111111------------")
+INST(thumb32_PLD_lit,        "PLD (lit)",                "11111000U00111111111iiiiiiiiiiii")
-//INST(thumb32_PLD_reg,        "PLD (reg)",                "111110000001----1111000000------")
+INST(thumb32_PLD_reg,        "PLD (reg)",                "1111100000W1nnnn1111000000iimmmm")
-//INST(thumb32_PLD_imm8,       "PLD (imm8)",               "1111100000-1----11111100--------")
+INST(thumb32_PLD_imm8,       "PLD (imm8)",               "1111100000W1nnnn11111100iiiiiiii")
-//INST(thumb32_PLD_imm12,      "PLD (imm12)",              "111110001001----1111------------")
+INST(thumb32_PLD_imm12,      "PLD (imm12)",              "1111100010W1nnnn1111iiiiiiiiiiii")
-//INST(thumb32_PLI_lit,        "PLI (lit)",                "11111001-00111111111------------")
+INST(thumb32_PLI_lit,        "PLI (lit)",                "11111001U00111111111iiiiiiiiiiii")
-//INST(thumb32_PLI_reg,        "PLI (reg)",                "111110010001----1111000000------")
+INST(thumb32_PLI_reg,        "PLI (reg)",                "111110010001nnnn1111000000iimmmm")
-//INST(thumb32_PLI_imm8,       "PLI (imm8)",               "111110010001----11111100--------")
+INST(thumb32_PLI_imm8,       "PLI (imm8)",               "111110010001nnnn11111100iiiiiiii")
-//INST(thumb32_PLI_imm12,      "PLI (imm12)",              "111110011001----1111------------")
+INST(thumb32_PLI_imm12,      "PLI (imm12)",              "111110011001nnnn1111iiiiiiiiiiii")
-//INST(thumb32_LDRB_lit,       "LDRB (lit)",               "11111000-0011111----------------")
+INST(thumb32_LDRB_lit,       "LDRB (lit)",               "11111000U0011111ttttiiiiiiiiiiii")
-//INST(thumb32_LDRB_reg,       "LDRB (reg)",               "111110000001--------000000------")
+INST(thumb32_LDRB_reg,       "LDRB (reg)",               "111110000001nnnntttt000000iimmmm")
-//INST(thumb32_LDRBT,          "LDRBT",                    "111110000001--------1110--------")
+INST(thumb32_LDRBT,          "LDRBT",                    "111110000001nnnntttt1110iiiiiiii")
-//INST(thumb32_LDRB_imm8,      "LDRB (imm8)",              "111110000001--------1-----------")
+INST(thumb32_LDRB_imm8,      "LDRB (imm8)",              "111110000001nnnntttt1PUWiiiiiiii")
-//INST(thumb32_LDRB_imm12,     "LDRB (imm12)",             "111110001001--------------------")
+INST(thumb32_LDRB_imm12,     "LDRB (imm12)",             "111110001001nnnnttttiiiiiiiiiiii")
-//INST(thumb32_LDRSB_lit,      "LDRSB (lit)",              "11111001-0011111----------------")
+INST(thumb32_LDRSB_lit,      "LDRSB (lit)",              "11111001U0011111ttttiiiiiiiiiiii")
-//INST(thumb32_LDRSB_reg,      "LDRSB (reg)",              "111110010001--------000000------")
+INST(thumb32_LDRSB_reg,      "LDRSB (reg)",              "111110010001nnnntttt000000iimmmm")
-//INST(thumb32_LDRSBT,         "LDRSBT",                   "111110010001--------1110--------")
+INST(thumb32_LDRSBT,         "LDRSBT",                   "111110010001nnnntttt1110iiiiiiii")
-//INST(thumb32_LDRSB_imm8,     "LDRSB (imm8)",             "111110010001--------1-----------")
+INST(thumb32_LDRSB_imm8,     "LDRSB (imm8)",             "111110010001nnnntttt1PUWiiiiiiii")
-//INST(thumb32_LDRSB_imm12,    "LDRSB (imm12)",            "111110011001--------------------")
+INST(thumb32_LDRSB_imm12,    "LDRSB (imm12)",            "111110011001nnnnttttiiiiiiiiiiii")
 
 // Load Halfword and Memory Hints
 //INST(thumb32_LDRH_lit,       "LDRH (lit)",               "11111000-0111111----------------")

src/frontend/A32/translate/impl/thumb32_load_byte.cpp

@@ -0,0 +1,210 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2021 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include <dynarmic/A32/config.h>
+#include "frontend/A32/translate/impl/translate_thumb.h"
+
+namespace Dynarmic::A32 {
+static bool PLDHandler(ThumbTranslatorVisitor& v, bool W) {
+    if (!v.options.hook_hint_instructions) {
+        return true;
+    }
+
+    const auto exception = W ? Exception::PreloadDataWithIntentToWrite
+                             : Exception::PreloadData;
+    return v.RaiseException(exception);
+}
+
+static bool PLIHandler(ThumbTranslatorVisitor& v) {
+    if (!v.options.hook_hint_instructions) {
+        return true;
+    }
+
+    return v.RaiseException(Exception::PreloadInstruction);
+}
+
+using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U8&);
+
+static bool LoadByteLiteral(ThumbTranslatorVisitor& v, bool U, Reg t, Imm<12> imm12,
+                            ExtensionFunction ext_fn) {
+    const u32 imm32 = imm12.ZeroExtend();
+    const u32 base = v.ir.AlignPC(4);
+    const u32 address = U ? (base + imm32) : (base - imm32);
+    const auto data = (v.ir.*ext_fn)(v.ir.ReadMemory8(v.ir.Imm32(address)));
+
+    v.ir.SetRegister(t, data);
+    return true;
+}
+
+static bool LoadByteRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m,
+                             ExtensionFunction ext_fn) {
+    if (m == Reg::PC) {
+        return v.UnpredictableInstruction();
+    }
+
+    const auto reg_n = v.ir.GetRegister(n);
+    const auto reg_m = v.ir.GetRegister(m);
+    const auto offset = v.ir.LogicalShiftLeft(reg_m, v.ir.Imm8(imm2.ZeroExtend<u8>()));
+    const auto address = v.ir.Add(reg_n, offset);
+    const auto data = (v.ir.*ext_fn)(v.ir.ReadMemory8(address));
+
+    v.ir.SetRegister(t, data);
+    return true;
+}
+
+static bool LoadByteImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W,
+                              Imm<12> imm12, ExtensionFunction ext_fn) {
+    const u32 imm32 = imm12.ZeroExtend();
+    const IR::U32 reg_n = v.ir.GetRegister(n);
+    const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32))
+                                     : v.ir.Sub(reg_n, v.ir.Imm32(imm32));
+    const IR::U32 address = P ? offset_address : reg_n;
+    const IR::U32 data = (v.ir.*ext_fn)(v.ir.ReadMemory8(address));
+
+    v.ir.SetRegister(t, data);
+    if (W) {
+        v.ir.SetRegister(n, offset_address);
+    }
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLD_lit([[maybe_unused]] bool U,
+                                             [[maybe_unused]] Imm<12> imm12) {
+    return PLDHandler(*this, false);
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLD_imm8(bool W,
+                                              [[maybe_unused]] Reg n,
+                                              [[maybe_unused]] Imm<8> imm8) {
+    return PLDHandler(*this, W);
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLD_imm12(bool W,
+                                               [[maybe_unused]] Reg n,
+                                               [[maybe_unused]] Imm<12> imm12) {
+    return PLDHandler(*this, W);
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLD_reg(bool W,
+                                             [[maybe_unused]] Reg n,
+                                             [[maybe_unused]] Imm<2> imm2,
+                                             Reg m) {
+    if (m == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    return PLDHandler(*this, W);
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLI_lit([[maybe_unused]] bool U,
+                                             [[maybe_unused]] Imm<12> imm12) {
+    return PLIHandler(*this);
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLI_imm8([[maybe_unused]] Reg n,
+                                              [[maybe_unused]] Imm<8> imm8) {
+    return PLIHandler(*this);
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLI_imm12([[maybe_unused]] Reg n,
+                                               [[maybe_unused]] Imm<12> imm12) {
+    return PLIHandler(*this);
+}
+
+bool ThumbTranslatorVisitor::thumb32_PLI_reg([[maybe_unused]] Reg n,
+                                             [[maybe_unused]] Imm<2> imm2,
+                                             Reg m) {
+    if (m == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    return PLIHandler(*this);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRB_lit(bool U, Reg t, Imm<12> imm12) {
+    return LoadByteLiteral(*this, U, t, imm12, &IREmitter::ZeroExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
+    if (t == Reg::PC && W) {
+        return UnpredictableInstruction();
+    }
+    if (W && n == t) {
+        return UnpredictableInstruction();
+    }
+    if (!P && !W) {
+        return UndefinedInstruction();
+    }
+
+    return LoadByteImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
+                             &IREmitter::ZeroExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12) {
+    return LoadByteImmediate(*this, n, t, true, true, false, imm12,
+                             &IREmitter::ZeroExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRB_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
+    return LoadByteRegister(*this, n, t, imm2, m, &IREmitter::ZeroExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8) {
+    // TODO: Add an unpredictable instruction path if this
+    //       is executed in hypervisor mode if we ever support
+    //       privileged execution modes.
+
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    // Treat it as a normal LDRB, given we don't support
+    // execution levels other than EL0 currently.
+    return thumb32_LDRB_imm8(n, t, true, true, false, imm8);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRSB_lit(bool U, Reg t, Imm<12> imm12) {
+    return LoadByteLiteral(*this, U, t, imm12, &IREmitter::SignExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRSB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
+    if (t == Reg::PC && W) {
+        return UnpredictableInstruction();
+    }
+    if (W && n == t) {
+        return UnpredictableInstruction();
+    }
+    if (!P && !W) {
+        return UndefinedInstruction();
+    }
+
+    return LoadByteImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
+                             &IREmitter::SignExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12) {
+    return LoadByteImmediate(*this, n, t, true, true, false, imm12,
+                             &IREmitter::SignExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRSB_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
+    return LoadByteRegister(*this, n, t, imm2, m, &IREmitter::SignExtendByteToWord);
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8) {
+    // TODO: Add an unpredictable instruction path if this
+    //       is executed in hypervisor mode if we ever support
+    //       privileged execution modes.
+
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    // Treat it as a normal LDRSB, given we don't support
+    // execution levels other than EL0 currently.
+    return thumb32_LDRSB_imm8(n, t, true, true, false, imm8);
+}
+
+} // namespace Dynarmic::A32

src/frontend/A32/translate/impl/thumb32_load_halfword.cpp

@@ -0,0 +1,11 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2021 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include "frontend/A32/translate/impl/translate_thumb.h"
+
+namespace Dynarmic::A32 {
+
+
+} // namespace Dynarmic::A32

src/frontend/A32/translate/impl/thumb32_load_word.cpp

@@ -0,0 +1,11 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2021 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include "frontend/A32/translate/impl/translate_thumb.h"
+
+namespace Dynarmic::A32 {
+
+
+} // namespace Dynarmic::A32

src/frontend/A32/translate/impl/translate_thumb.h

@@ -207,6 +207,26 @@ struct ThumbTranslatorVisitor final {
     bool thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m);
     bool thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
 
+    // thumb32 load byte and memory hints
+    bool thumb32_PLD_lit(bool U, Imm<12> imm12);
+    bool thumb32_PLD_imm8(bool W, Reg n, Imm<8> imm8);
+    bool thumb32_PLD_imm12(bool W, Reg n, Imm<12> imm12);
+    bool thumb32_PLD_reg(bool W, Reg n, Imm<2> imm2, Reg m);
+    bool thumb32_PLI_lit(bool U, Imm<12> imm12);
+    bool thumb32_PLI_imm8(Reg n, Imm<8> imm8);
+    bool thumb32_PLI_imm12(Reg n, Imm<12> imm12);
+    bool thumb32_PLI_reg(Reg n, Imm<2> imm2, Reg m);
+    bool thumb32_LDRB_lit(bool U, Reg t, Imm<12> imm12);
+    bool thumb32_LDRB_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
+    bool thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
+    bool thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12);
+    bool thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8);
+    bool thumb32_LDRSB_lit(bool U, Reg t, Imm<12> imm12);
+    bool thumb32_LDRSB_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
+    bool thumb32_LDRSB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
+    bool thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12);
+    bool thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8);
+
     // thumb32 data processing (register) instructions
     bool thumb32_ASR_reg(Reg m, Reg d, Reg s);
     bool thumb32_LSL_reg(Reg m, Reg d, Reg s);