IR: Implement A64OrQC
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5 changed files with 22 additions and 0 deletions
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@ -468,6 +468,21 @@ void A64EmitX64::EmitA64SetFPSR(A64EmitContext& ctx, IR::Inst* inst) {
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code.ldmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
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}
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void A64EmitX64::EmitA64OrQC(A64EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (args[0].IsImmediate()) {
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if (!args[0].GetImmediateU1())
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return;
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code.mov(code.byte[code.r15 + offsetof(A64JitState, fpsr_qc)], u8(1));
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return;
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}
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const Xbyak::Reg8 to_store = ctx.reg_alloc.UseGpr(args[1]).cvt8();
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code.or_(code.byte[code.r15 + offsetof(A64JitState, fpsr_qc)], to_store);
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}
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void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto addr = qword[r15 + offsetof(A64JitState, pc)];
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@ -33,6 +33,10 @@ void IREmitter::SetNZCV(const IR::NZCV& nzcv) {
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Inst(Opcode::A64SetNZCV, nzcv);
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}
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void IREmitter::OrQC(const IR::U1& value) {
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Inst(Opcode::A64OrQC, value);
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}
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void IREmitter::CallSupervisor(u32 imm) {
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Inst(Opcode::A64CallSupervisor, Imm32(imm));
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}
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@ -38,6 +38,7 @@ public:
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void SetCheckBit(const IR::U1& value);
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IR::U1 GetCFlag();
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void SetNZCV(const IR::NZCV& nzcv);
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void OrQC(const IR::U1& value);
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void CallSupervisor(u32 imm);
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void ExceptionRaised(Exception exception);
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@ -341,6 +341,7 @@ bool Inst::ReadsFromFPSRCumulativeSaturationBit() const {
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bool Inst::WritesToFPSRCumulativeSaturationBit() const {
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switch (op) {
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case Opcode::A64OrQC:
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case Opcode::VectorSignedSaturatedNarrowToSigned16:
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case Opcode::VectorSignedSaturatedNarrowToSigned32:
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case Opcode::VectorSignedSaturatedNarrowToSigned64:
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@ -59,6 +59,7 @@ A64OPC(SetQ, T::Void, T::A64Vec,
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A64OPC(SetSP, T::Void, T::U64 )
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A64OPC(SetFPCR, T::Void, T::U32 )
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A64OPC(SetFPSR, T::Void, T::U32 )
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A64OPC(OrQC, T::Void, T::U1 )
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A64OPC(SetPC, T::Void, T::U64 )
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A64OPC(CallSupervisor, T::Void, T::U32 )
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A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )
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