A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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MerryMage
parent
6414736a8d
commit
ed2bedec43
5 changed files with 133 additions and 36 deletions
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@ -77,6 +77,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/impl.cpp
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frontend/A64/translate/impl/impl.cpp
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frontend/A64/translate/impl/impl.h
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frontend/A64/translate/impl/impl.h
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frontend/A64/translate/impl/load_store_load_literal.cpp
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frontend/A64/translate/impl/load_store_load_literal.cpp
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frontend/A64/translate/impl/load_store_multiple_structures.cpp
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frontend/A64/translate/impl/load_store_register_immediate.cpp
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frontend/A64/translate/impl/load_store_register_immediate.cpp
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frontend/A64/translate/impl/load_store_register_pair.cpp
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frontend/A64/translate/impl/load_store_register_pair.cpp
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frontend/A64/translate/impl/load_store_register_unprivileged.cpp
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frontend/A64/translate/impl/load_store_register_unprivileged.cpp
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@ -92,22 +92,10 @@ INST(TBZ, "TBZ", "b0110
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INST(TBNZ, "TBNZ", "b0110111bbbbbiiiiiiiiiiiiiittttt")
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INST(TBNZ, "TBNZ", "b0110111bbbbbiiiiiiiiiiiiiittttt")
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// Loads and stores - Advanced SIMD Load/Store multiple structures
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// Loads and stores - Advanced SIMD Load/Store multiple structures
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//INST(ST4_mult_1, "ST4 (multiple structures)", "0Q001100000000000000zznnnnnttttt")
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INST(STx_mult_1, "STx (multiple structures)", "0Q00110000000000oooozznnnnnttttt")
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//INST(ST4_mult_2, "ST4 (multiple structures)", "0Q001100100mmmmm0000zznnnnnttttt")
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INST(STx_mult_2, "STx (multiple structures)", "0Q001100100mmmmmoooozznnnnnttttt")
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//INST(ST1_mult_1, "ST1 (multiple structures)", "0Q00110000000000--1-zznnnnnttttt")
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INST(LDx_mult_1, "LDx (multiple structures)", "0Q00110001000000oooozznnnnnttttt")
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//INST(ST1_mult_2, "ST1 (multiple structures)", "0Q001100100mmmmm--1-zznnnnnttttt")
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INST(LDx_mult_2, "LDx (multiple structures)", "0Q001100110mmmmmoooozznnnnnttttt")
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//INST(ST3_mult_1, "ST3 (multiple structures)", "0Q001100000000000100zznnnnnttttt")
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//INST(ST3_mult_2, "ST3 (multiple structures)", "0Q001100100mmmmm0100zznnnnnttttt")
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//INST(ST2_mult_1, "ST2 (multiple structures)", "0Q001100000000001000zznnnnnttttt")
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//INST(ST2_mult_2, "ST2 (multiple structures)", "0Q001100100mmmmm1000zznnnnnttttt")
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//INST(LD4_mult_1, "LD4 (multiple structures)", "0Q001100010000000000zznnnnnttttt")
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//INST(LD4_mult_2, "LD4 (multiple structures)", "0Q001100110mmmmm0000zznnnnnttttt")
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//INST(LD1_mult_1, "LD1 (multiple structures)", "0Q00110001000000--1-zznnnnnttttt")
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//INST(LD1_mult_2, "LD1 (multiple structures)", "0Q001100110mmmmm--1-zznnnnnttttt")
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//INST(LD3_mult_1, "LD3 (multiple structures)", "0Q001100010000000100zznnnnnttttt")
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//INST(LD3_mult_2, "LD3 (multiple structures)", "0Q001100110mmmmm0100zznnnnnttttt")
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//INST(LD2_mult_1, "LD2 (multiple structures)", "0Q001100010000001000zznnnnnttttt")
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//INST(LD2_mult_2, "LD2 (multiple structures)", "0Q001100110mmmmm1000zznnnnnttttt")
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// Loads and stores - Advanced SIMD Load/Store single structures
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// Loads and stores - Advanced SIMD Load/Store single structures
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//INST(ST1_sngl_1, "ST1 (single structure)", "0Q00110100000000--0Szznnnnnttttt")
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//INST(ST1_sngl_1, "ST1 (single structure)", "0Q00110100000000--0Szznnnnnttttt")
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@ -152,22 +152,10 @@ struct TranslatorVisitor final {
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bool TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt);
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bool TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt);
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// Loads and stores - Advanced SIMD Load/Store multiple structures
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// Loads and stores - Advanced SIMD Load/Store multiple structures
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bool ST4_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool STx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt);
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bool ST4_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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bool STx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt);
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bool ST1_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool LDx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt);
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bool ST1_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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bool LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt);
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bool ST3_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool ST3_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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bool ST2_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool ST2_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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bool LD4_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool LD4_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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bool LD1_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool LD1_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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bool LD3_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool LD3_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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bool LD2_mult_1(bool Q, Imm<2> size, Reg Rn, Reg Rt);
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bool LD2_mult_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Reg Rt);
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// Loads and stores - Advanced SIMD Load/Store single structures
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// Loads and stores - Advanced SIMD Load/Store single structures
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bool ST1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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@ -0,0 +1,120 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <tuple>
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#include <boost/optional.hpp>
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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static bool SharedDecodeAndOperation(TranslatorVisitor& tv, IREmitter& ir, bool wback, MemOp memop, bool Q, boost::optional<Reg> Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t elements = datasize / esize;
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const size_t ebytes = esize / 8;
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size_t rpt, selem;
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switch (opcode.ZeroExtend()) {
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case 0b0000:
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rpt = 1;
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selem = 4;
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break;
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case 0b0010:
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rpt = 4;
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selem = 1;
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break;
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case 0b0100:
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rpt = 1;
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selem = 3;
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break;
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case 0b0110:
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rpt = 3;
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selem = 1;
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break;
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case 0b0111:
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rpt = 1;
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selem = 1;
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break;
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case 0b1000:
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rpt = 1;
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selem = 2;
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break;
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case 0b1010:
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rpt = 2;
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selem = 1;
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break;
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default:
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return tv.UnallocatedEncoding();
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}
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if ((size == 0b11 && !Q) && selem != 1) {
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return tv.ReservedValue();
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}
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IR::U64 address;
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if (Rn == Reg::SP)
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// TODO: Check SP Alignment
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address = tv.SP(64);
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else
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address = tv.X(64, Rn);
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IR::U64 offs = ir.Imm64(0);
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for (size_t r = 0; r < rpt; r++) {
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for (size_t e = 0; e < elements; e++) {
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for (size_t s = 0; s < selem; s++) {
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const Vec tt = static_cast<Vec>((VecNumber(Vt) + r + s) % 32);
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if (memop == MemOp::LOAD) {
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const IR::UAny elem = tv.Mem(ir.Add(address, offs), ebytes, AccType::VEC);
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const IR::U128 vec = ir.VectorSetElement(esize, tv.V(datasize, tt), e, elem);
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tv.V(datasize, tt, vec);
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} else {
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const IR::UAny elem = ir.VectorGetElement(esize, tv.V(datasize, tt), e);
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tv.Mem(ir.Add(address, offs), ebytes, AccType::VEC, elem);
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}
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offs = ir.Add(offs, ir.Imm64(ebytes));
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}
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}
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}
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if (wback) {
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if (*Rm != Reg::SP)
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offs = tv.X(64, *Rm);
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if (Rn == Reg::SP)
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tv.SP(64, ir.Add(address, offs));
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else
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tv.X(64, Rn, ir.Add(address, offs));
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}
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return true;
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}
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bool TranslatorVisitor::STx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
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const bool wback = false;
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const MemOp memop = MemOp::STORE;
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return SharedDecodeAndOperation(*this, ir, wback, memop, Q, {}, opcode, size, Rn, Vt);
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}
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bool TranslatorVisitor::STx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
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const bool wback = true;
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const MemOp memop = MemOp::STORE;
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return SharedDecodeAndOperation(*this, ir, wback, memop, Q, Rm, opcode, size, Rn, Vt);
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}
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bool TranslatorVisitor::LDx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
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const bool wback = false;
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const MemOp memop = MemOp::LOAD;
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return SharedDecodeAndOperation(*this, ir, wback, memop, Q, {}, opcode, size, Rn, Vt);
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}
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bool TranslatorVisitor::LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
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const bool wback = true;
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const MemOp memop = MemOp::LOAD;
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return SharedDecodeAndOperation(*this, ir, wback, memop, Q, Rm, opcode, size, Rn, Vt);
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}
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} // namespace Dynarmic::A64
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@ -187,10 +187,10 @@ OPCODE(VectorGetElement8, T::U8, T::U128, T::U8
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OPCODE(VectorGetElement16, T::U16, T::U128, T::U8 )
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OPCODE(VectorGetElement16, T::U16, T::U128, T::U8 )
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OPCODE(VectorGetElement32, T::U32, T::U128, T::U8 )
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OPCODE(VectorGetElement32, T::U32, T::U128, T::U8 )
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OPCODE(VectorGetElement64, T::U64, T::U128, T::U8 )
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OPCODE(VectorGetElement64, T::U64, T::U128, T::U8 )
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OPCODE(VectorSetElement8, T::U128, T::U128, T::U8, T::U8 )
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OPCODE(VectorSetElement8, T::U128, T::U128, T::U8, T::U8 )
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OPCODE(VectorSetElement16, T::U128, T::U128, T::U8, T::U16 )
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OPCODE(VectorSetElement16, T::U128, T::U128, T::U8, T::U16 )
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OPCODE(VectorSetElement32, T::U128, T::U128, T::U8, T::U32 )
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OPCODE(VectorSetElement32, T::U128, T::U128, T::U8, T::U32 )
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OPCODE(VectorSetElement64, T::U128, T::U128, T::U8, T::U64 )
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OPCODE(VectorSetElement64, T::U128, T::U128, T::U8, T::U64 )
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OPCODE(VectorAdd8, T::U128, T::U128, T::U128 )
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OPCODE(VectorAdd8, T::U128, T::U128, T::U128 )
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OPCODE(VectorAdd16, T::U128, T::U128, T::U128 )
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OPCODE(VectorAdd16, T::U128, T::U128, T::U128 )
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OPCODE(VectorAdd32, T::U128, T::U128, T::U128 )
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OPCODE(VectorAdd32, T::U128, T::U128, T::U128 )
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