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A64: Implement UHSUB

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Lioncash 2018-05-07 12:50:47 -04:00 committed by MerryMage
parent b33360a324
commit f2a85d5601
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -744,7 +744,7 @@ INST(ORN_asimd, "ORN (vector)", "0Q001
INST(UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd")
//INST(UQADD_2, "UQADD", "0Q101110zz1mmmmm000011nnnnnddddd")
//INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd")
//INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd")
INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd")
//INST(UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd")
INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd")
INST(CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -231,6 +231,22 @@ bool TranslatorVisitor::UHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::UHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 8 << size.ZeroExtend();
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorHalvingSubUnsigned(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();