load_store: Simplify implementation
* Remove dead code * Standardise code style with rest of code base
This commit is contained in:
MerryMage
parent
058f7b5de6
commit
f2dd82967f
1 changed files with 177 additions and 265 deletions
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@ -41,50 +41,38 @@ bool ArmTranslatorVisitor::arm_STRT() {
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ASSERT_MSG(false, "System instructions unimplemented");
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}
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static IR::Value GetAddressingMode(IR::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::Value index) {
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IR::Value address;
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if (P) {
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// Pre-indexed addressing
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if (n == Reg::PC && index.IsImmediate()) {
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address = U ? ir.Imm32(ir.AlignPC(4) + index.GetU32()) : ir.Imm32(ir.AlignPC(4) - index.GetU32());
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} else {
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address = U ? ir.Add(ir.GetRegister(n), index) : ir.Sub(ir.GetRegister(n), index);
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}
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static IR::Value GetAddress(IR::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::Value offset) {
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const bool index = P;
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const bool add = U;
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const bool wback = !P || W;
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// Wrote calculated address back to the base register
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if (W) {
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ir.SetRegister(n, address);
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}
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} else {
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// Post-indexed addressing
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address = (n == Reg::PC) ? ir.Imm32(ir.AlignPC(4)) : ir.GetRegister(n);
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const auto offset_addr = add ? ir.Add(ir.GetRegister(n), offset) : ir.Sub(ir.GetRegister(n), offset);
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const auto address = index ? offset_addr : ir.GetRegister(n);
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if (U) {
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ir.SetRegister(n, ir.Add(ir.GetRegister(n), index));
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} else {
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ir.SetRegister(n, ir.Sub(ir.GetRegister(n), index));
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}
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// TODO(bunnei): Handle W=1 mode, which in this scenario does an unprivileged (User mode) access.
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if (wback) {
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ir.SetRegister(n, offset_addr);
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}
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return address;
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}
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bool ArmTranslatorVisitor::arm_LDR_lit(Cond cond, bool U, Reg t, Imm12 imm12) {
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bool P = true, W = false;
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const bool add = U;
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// LDR <Rt>, [PC, #+/-<imm>]
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if (ConditionPassed(cond)) {
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const auto data = ir.ReadMemory32(GetAddressingMode(ir, P, U, W, Reg::PC, ir.Imm32(imm12)));
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm12) : (base - imm12);
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const auto data = ir.ReadMemory32(ir.Imm32(address));
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if (t == Reg::PC) {
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ir.BXWritePC(data);
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ir.LoadWritePC(data);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -95,11 +83,17 @@ bool ArmTranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n,
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if ((!P || W) && n == t)
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return UnpredictableInstruction();
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const u32 imm32 = imm12;
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// LDR <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDR <Rt>, [<Rn>], #+/-<imm>
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if (ConditionPassed(cond)) {
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const auto data = ir.ReadMemory32(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12)));
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const auto offset = ir.Imm32(imm32);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ReadMemory32(address);
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if (t == Reg::PC) {
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ir.BXWritePC(data);
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ir.LoadWritePC(data);
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if (!P && W && n == Reg::R13)
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ir.SetTerm(IR::Term::PopRSBHint{});
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else
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@ -109,7 +103,6 @@ bool ArmTranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n,
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -120,19 +113,21 @@ bool ArmTranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n,
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if ((!P || W) && (n == Reg::PC || n == t))
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return UnpredictableInstruction();
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// LDR <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDR <Rt>, [<Rn>], #+/-<Rm>
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if (ConditionPassed(cond)) {
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const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
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const auto data = ir.ReadMemory32(GetAddressingMode(ir, P, U, W, n, shifted.result));
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const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ReadMemory32(address);
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if (t == Reg::PC) {
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ir.BXWritePC(data);
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ir.LoadWritePC(data);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -140,19 +135,17 @@ bool ArmTranslatorVisitor::arm_LDRB_lit(Cond cond, bool U, Reg t, Imm12 imm12) {
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if (t == Reg::PC)
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return UnpredictableInstruction();
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bool P = true, W = false;
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if (ConditionPassed(cond)) {
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, Reg::PC, ir.Imm32(imm12))));
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const u32 imm32 = imm12;
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const bool add = U;
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if (t == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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// LDRB <Rt>, [PC, #+/-<imm>]
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if (ConditionPassed(cond)) {
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(ir.Imm32(address)));
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -165,18 +158,17 @@ bool ArmTranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n
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if (t == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12))));
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const u32 imm32 = imm12;
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if (t == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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// LDRB <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRB <Rt>, [<Rn>], #+/-<imm>
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if (ConditionPassed(cond)) {
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const auto offset = ir.Imm32(imm32);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -187,19 +179,15 @@ bool ArmTranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n
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if ((!P || W) && (n == Reg::PC || n == t))
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return UnpredictableInstruction();
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// LDRB <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDRB <Rt>, [<Rn>], #+/-<Rm>
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if (ConditionPassed(cond)) {
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const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, shifted.result)));
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if (t == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -209,43 +197,20 @@ bool ArmTranslatorVisitor::arm_LDRD_lit(Cond cond, bool U, Reg t, Imm4 imm8a, Im
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if (t+1 == Reg::PC)
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return UnpredictableInstruction();
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bool P = true, W = false;
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const Reg t2 = t+1;
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const u32 imm32 = (imm8a << 4) | imm8b;
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const bool add = U;
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// LDRD <Rt>, <Rt2>, [PC, #+/-<imm>]
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if (ConditionPassed(cond)) {
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const auto address_a = GetAddressingMode(ir, P, U, W, Reg::PC, ir.Imm32(imm8a << 4 | imm8b));
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const auto address_b = ir.Add(address_a, ir.Imm32(4));
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auto data_a = ir.ReadMemory32(address_a);
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auto data_b = ir.ReadMemory32(address_b);
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data_a = ir.ReadMemory32(ir.Imm32(address));
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const auto data_b = ir.ReadMemory32(ir.Imm32(address + 4));
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switch (t) {
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case Reg::PC:
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data_a = ir.Add(data_a, ir.Imm32(4));
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break;
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case Reg::LR:
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data_b = ir.Add(data_b, ir.Imm32(4));
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break;
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default:
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break;
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}
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if (t == Reg::PC) {
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ir.ALUWritePC(data_a);
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} else {
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ir.SetRegister(t, data_a);
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}
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const Reg reg_b = static_cast<Reg>(std::min(t + 1, Reg::R15));
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if (reg_b == Reg::PC) {
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ir.ALUWritePC(data_b);
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} else {
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ir.SetRegister(reg_b, data_b);
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}
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if (t == Reg::PC || reg_b == Reg::PC) {
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(t, data_a);
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ir.SetRegister(t2, data_b);
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}
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return true;
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}
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@ -261,42 +226,21 @@ bool ArmTranslatorVisitor::arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n
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if (t+1 == Reg::PC)
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return UnpredictableInstruction();
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const Reg t2 = t+1;
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const u32 imm32 = (imm8a << 4) | imm8b;
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// LDRD <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRD <Rt>, [<Rn>], #+/-<imm>
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if (ConditionPassed(cond)) {
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const auto address_a = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b));
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const auto offset = ir.Imm32(imm32);
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const auto address_a = GetAddress(ir, P, U, W, n, offset);
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const auto address_b = ir.Add(address_a, ir.Imm32(4));
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auto data_a = ir.ReadMemory32(address_a);
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auto data_b = ir.ReadMemory32(address_b);
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const auto data_a = ir.ReadMemory32(address_a);
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const auto data_b = ir.ReadMemory32(address_b);
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switch (t) {
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case Reg::PC:
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data_a = ir.Add(data_a, ir.Imm32(4));
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break;
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case Reg::LR:
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data_b = ir.Add(data_b, ir.Imm32(4));
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break;
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default:
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break;
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}
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if (t == Reg::PC) {
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ir.ALUWritePC(data_a);
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} else {
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ir.SetRegister(t, data_a);
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}
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const Reg reg_b = static_cast<Reg>(std::min(t + 1, Reg::R15));
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if (reg_b == Reg::PC) {
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ir.ALUWritePC(data_b);
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} else {
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ir.SetRegister(reg_b, data_b);
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}
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if (t == Reg::PC || reg_b == Reg::PC) {
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(t, data_a);
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ir.SetRegister(t2, data_b);
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}
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return true;
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}
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@ -310,42 +254,20 @@ bool ArmTranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n
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if ((!P || W) && (n == Reg::PC || n == t || n == t+1))
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return UnpredictableInstruction();
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const Reg t2 = t+1;
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// LDRD <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDRD <Rt>, [<Rn>], #+/-<Rm>
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if (ConditionPassed(cond)) {
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const auto address_a = GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m));
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const auto offset = ir.GetRegister(m);
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const auto address_a = GetAddress(ir, P, U, W, n, offset);
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const auto address_b = ir.Add(address_a, ir.Imm32(4));
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auto data_a = ir.ReadMemory32(address_a);
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auto data_b = ir.ReadMemory32(address_b);
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const auto data_a = ir.ReadMemory32(address_a);
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const auto data_b = ir.ReadMemory32(address_b);
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switch (t) {
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case Reg::PC:
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data_a = ir.Add(data_a, ir.Imm32(4));
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break;
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case Reg::LR:
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data_b = ir.Add(data_b, ir.Imm32(4));
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break;
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default:
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break;
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}
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if (t == Reg::PC) {
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ir.ALUWritePC(data_a);
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} else {
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ir.SetRegister(t, data_a);
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}
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const Reg reg_b = static_cast<Reg>(std::min(t + 1, Reg::R15));
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if (reg_b == Reg::PC) {
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ir.ALUWritePC(data_b);
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} else {
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ir.SetRegister(reg_b, data_b);
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}
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if (t == Reg::PC || reg_b == Reg::PC) {
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(t, data_a);
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ir.SetRegister(t2, data_b);
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}
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return true;
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}
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@ -356,18 +278,17 @@ bool ArmTranslatorVisitor::arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t
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if (t == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, Reg::PC, ir.Imm32(imm8a << 4 | imm8b))));
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const u32 imm32 = (imm8a << 4) | imm8b;
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const bool add = U;
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if (t == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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// LDRH <Rt>, [PC, #-/+<imm>]
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if (ConditionPassed(cond)) {
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(ir.Imm32(address)));
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -380,18 +301,17 @@ bool ArmTranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n
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if (t == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b))));
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const u32 imm32 = (imm8a << 4) | imm8b;
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if (t == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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// LDRH <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRH <Rt>, [<Rn>], #+/-<imm>
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if (ConditionPassed(cond)) {
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const auto offset = ir.Imm32(imm32);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
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ir.SetRegister(t, data);
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}
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return true;
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}
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@ -402,18 +322,15 @@ bool ArmTranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n
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if ((!P || W) && (n == Reg::PC || n == t))
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return UnpredictableInstruction();
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// LDRH <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDRH <Rt>, [<Rn>], #+/-<Rm>
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if (ConditionPassed(cond)) {
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m))));
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if (t == Reg::PC) {
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ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
|
||||
return false;
|
||||
}
|
||||
const auto offset = ir.GetRegister(m);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
|
||||
|
||||
ir.SetRegister(t, data);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -421,19 +338,17 @@ bool ArmTranslatorVisitor::arm_LDRSB_lit(Cond cond, bool U, Reg t, Imm4 imm8a, I
|
|||
if (t == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
bool P = true, W = false;
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, Reg::PC, ir.Imm32(imm8a << 4 | imm8b))));
|
||||
const u32 imm32 = (imm8a << 4) | imm8b;
|
||||
const bool add = U;
|
||||
|
||||
if (t == Reg::PC) {
|
||||
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
|
||||
ir.SetTerm(IR::Term::ReturnToDispatch{});
|
||||
return false;
|
||||
}
|
||||
// LDRSB <Rt>, [PC, #+/-<imm>]
|
||||
if (ConditionPassed(cond)) {
|
||||
const u32 base = ir.AlignPC(4);
|
||||
const u32 address = add ? (base + imm32) : (base - imm32);
|
||||
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(ir.Imm32(address)));
|
||||
|
||||
ir.SetRegister(t, data);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -446,18 +361,17 @@ bool ArmTranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg
|
|||
if (t == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b))));
|
||||
const u32 imm32 = (imm8a << 4) | imm8b;
|
||||
|
||||
if (t == Reg::PC) {
|
||||
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
|
||||
ir.SetTerm(IR::Term::ReturnToDispatch{});
|
||||
return false;
|
||||
}
|
||||
// LDRSB <Rt>, [<Rn>, #+/-<imm>]{!}
|
||||
// LDRSB <Rt>, [<Rn>], #+/-<imm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto offset = ir.Imm32(imm32);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(address));
|
||||
|
||||
ir.SetRegister(t, data);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -468,18 +382,15 @@ bool ArmTranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg
|
|||
if ((!P || W) && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// LDRSB <Rt>, [<Rn>, #+/-<Rm>]{!}
|
||||
// LDRSB <Rt>, [<Rn>], #+/-<Rm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m))));
|
||||
|
||||
if (t == Reg::PC) {
|
||||
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
|
||||
ir.SetTerm(IR::Term::ReturnToDispatch{});
|
||||
return false;
|
||||
}
|
||||
const auto offset = ir.GetRegister(m);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(address));
|
||||
|
||||
ir.SetRegister(t, data);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -487,19 +398,17 @@ bool ArmTranslatorVisitor::arm_LDRSH_lit(Cond cond, bool U, Reg t, Imm4 imm8a, I
|
|||
if (t == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
bool P = true, W = false;
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, Reg::PC, ir.Imm32(imm8a << 4 | imm8b))));
|
||||
const u32 imm32 = (imm8a << 4) | imm8b;
|
||||
const bool add = U;
|
||||
|
||||
if (t == Reg::PC) {
|
||||
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
|
||||
ir.SetTerm(IR::Term::ReturnToDispatch{});
|
||||
return false;
|
||||
}
|
||||
// LDRSH <Rt>, [PC, #-/+<imm>]
|
||||
if (ConditionPassed(cond)) {
|
||||
const u32 base = ir.AlignPC(4);
|
||||
const u32 address = add ? (base + imm32) : (base - imm32);
|
||||
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(ir.Imm32(address)));
|
||||
|
||||
ir.SetRegister(t, data);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -512,18 +421,17 @@ bool ArmTranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg
|
|||
if (t == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b))));
|
||||
const u32 imm32 = (imm8a << 4) | imm8b;
|
||||
|
||||
if (t == Reg::PC) {
|
||||
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
|
||||
ir.SetTerm(IR::Term::ReturnToDispatch{});
|
||||
return false;
|
||||
}
|
||||
// LDRSH <Rt>, [<Rn>, #+/-<imm>]{!}
|
||||
// LDRSH <Rt>, [<Rn>], #+/-<imm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto offset = ir.Imm32(imm32);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(address));
|
||||
|
||||
ir.SetRegister(t, data);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -534,18 +442,15 @@ bool ArmTranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg
|
|||
if ((!P || W) && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// LDRSH <Rt>, [<Rn>, #+/-<Rm>]{!}
|
||||
// LDRSH <Rt>, [<Rn>], #+/-<Rm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m))));
|
||||
|
||||
if (t == Reg::PC) {
|
||||
ir.ALUWritePC(ir.Add(data, ir.Imm32(4)));
|
||||
ir.SetTerm(IR::Term::ReturnToDispatch{});
|
||||
return false;
|
||||
}
|
||||
const auto offset = ir.GetRegister(m);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(address));
|
||||
|
||||
ir.SetRegister(t, data);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -553,11 +458,13 @@ bool ArmTranslatorVisitor::arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n,
|
|||
if (W && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// STR <Rt>, [<Rn>, #+/-<imm>]{!}
|
||||
// STR <Rt>, [<Rn>], #+/-<imm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12));
|
||||
const auto offset = ir.Imm32(imm12);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
ir.WriteMemory32(address, ir.GetRegister(t));
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -568,12 +475,13 @@ bool ArmTranslatorVisitor::arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n,
|
|||
if (W && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// STR <Rt>, [<Rn>, #+/-<Rm>]{!}
|
||||
// STR <Rt>, [<Rn>], #+/-<Rm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
|
||||
const auto address = GetAddressingMode(ir, P, U, W, n, shifted.result);
|
||||
const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
ir.WriteMemory32(address, ir.GetRegister(t));
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -584,12 +492,13 @@ bool ArmTranslatorVisitor::arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n
|
|||
if (W && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// STRB <Rt>, [<Rn>, #+/-<imm>]{!}
|
||||
// STRB <Rt>, [<Rn>], #+/-<imm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12));
|
||||
const auto value = (t == Reg::PC) ? ir.Imm8(static_cast<u8>(ir.PC() - 8)) : ir.GetRegister(t);
|
||||
ir.WriteMemory8(address, ir.LeastSignificantByte(value));
|
||||
const auto offset = ir.Imm32(imm12);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
ir.WriteMemory8(address, ir.LeastSignificantByte(ir.GetRegister(t)));
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -600,47 +509,47 @@ bool ArmTranslatorVisitor::arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n
|
|||
if (W && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// STRB <Rt>, [<Rn>, #+/-<Rm>]{!}
|
||||
// STRB <Rt>, [<Rn>], #+/-<Rm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
|
||||
const auto address = GetAddressingMode(ir, P, U, W, n, shifted.result);
|
||||
const auto value = (t == Reg::PC) ? ir.Imm8(static_cast<u8>(ir.PC() - 8)) : ir.GetRegister(t);
|
||||
ir.WriteMemory8(address, ir.LeastSignificantByte(value));
|
||||
const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
ir.WriteMemory8(address, ir.LeastSignificantByte(ir.GetRegister(t)));
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
if (size_t(t) % 2 != 0)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (!P && W)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
const u32 imm32 = imm8a << 4 | imm8b;
|
||||
const Reg t2 = t + 1;
|
||||
|
||||
if (W && (n == Reg::PC || n == t || n == t2))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (t2 == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// STRD <Rt>, [<Rn>, #+/-<imm>]{!}
|
||||
// STRD <Rt>, [<Rn>], #+/-<imm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto address_a = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b));
|
||||
const auto offset = ir.Imm32(imm32);
|
||||
const auto address_a = GetAddress(ir, P, U, W, n, offset);
|
||||
const auto address_b = ir.Add(address_a, ir.Imm32(4));
|
||||
const auto value_a = ir.GetRegister(t);
|
||||
const auto value_b = ir.GetRegister(t2);
|
||||
ir.WriteMemory32(address_a, value_a);
|
||||
ir.WriteMemory32(address_b, value_b);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (size_t(t) % 2 != 0)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (!P && W)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
|
|
@ -648,51 +557,54 @@ bool ArmTranslatorVisitor::arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n
|
|||
|
||||
if (t2 == Reg::PC || m == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (W && (n == Reg::PC || n == t || n == t2))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// STRD <Rt>, [<Rn>, #+/-<Rm>]{!}
|
||||
// STRD <Rt>, [<Rn>], #+/-<Rm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto address_a = GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m));
|
||||
const auto offset = ir.GetRegister(m);
|
||||
const auto address_a = GetAddress(ir, P, U, W, n, offset);
|
||||
const auto address_b = ir.Add(address_a, ir.Imm32(4));
|
||||
const auto value_a = ir.GetRegister(t);
|
||||
const auto value_b = ir.GetRegister(t2);
|
||||
ir.WriteMemory32(address_a, value_a);
|
||||
ir.WriteMemory32(address_b, value_b);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
if (t == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (W && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b));
|
||||
const auto value = (t == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(t);
|
||||
ir.WriteMemory16(address, ir.LeastSignificantHalf(value));
|
||||
}
|
||||
const u32 imm32 = imm8a << 4 | imm8b;
|
||||
|
||||
// STRH <Rt>, [<Rn>, #+/-<imm>]{!}
|
||||
// STRH <Rt>, [<Rn>], #+/-<imm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto offset = ir.Imm32(imm32);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
ir.WriteMemory16(address, ir.LeastSignificantHalf(ir.GetRegister(t)));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (t == Reg::PC || m == Reg::PC)
|
||||
return UnpredictableInstruction();
|
||||
|
||||
if (W && (n == Reg::PC || n == t))
|
||||
return UnpredictableInstruction();
|
||||
|
||||
// STRH <Rt>, [<Rn>, #+/-<Rm>]{!}
|
||||
// STRH <Rt>, [<Rn>], #+/-<Rm>
|
||||
if (ConditionPassed(cond)) {
|
||||
const auto address = GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m));
|
||||
const auto value = (t == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(t);
|
||||
ir.WriteMemory16(address, ir.LeastSignificantHalf(value));
|
||||
const auto offset = ir.GetRegister(m);
|
||||
const auto address = GetAddress(ir, P, U, W, n, offset);
|
||||
ir.WriteMemory16(address, ir.LeastSignificantHalf(ir.GetRegister(t)));
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue