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IR: Implement VectorGreaterSigned

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This commit is contained in:
MerryMage 2018-02-13 14:06:54 +00:00
parent 1f5b3bca43
commit f4775910f5
4 changed files with 45 additions and 0 deletions
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25
src/backend_x64/emit_x64_vector.cpp
View file

@ -485,6 +485,31 @@ void EmitX64::EmitVectorEqual128(EmitContext& ctx, IR::Inst* inst) {
}
}
void EmitX64::EmitVectorGreaterS8(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pcmpgtb);
}
void EmitX64::EmitVectorGreaterS16(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pcmpgtw);
}
void EmitX64::EmitVectorGreaterS32(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pcmpgtd);
}
void EmitX64::EmitVectorGreaterS64(EmitContext& ctx, IR::Inst* inst) {
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::pcmpgtq);
return;
}
EmitTwoArgumentFallback(code, ctx, inst, [](std::array<u64, 2>& result, const std::array<s64, 2>& a, const std::array<s64, 2>& b){
for (size_t i = 0; i < 2; ++i) {
result[i] = (a[i] > b[i]) ? ~u64(0) : 0;
}
});
}
static void EmitVectorInterleaveLower(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int size) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

15
src/frontend/ir/ir_emitter.cpp
View file

@ -872,6 +872,21 @@ U128 IREmitter::VectorEqual(size_t esize, const U128& a, const U128& b) {
return {};
}
U128 IREmitter::VectorGreaterSigned(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorGreaterS8, a, b);
case 16:
return Inst<U128>(Opcode::VectorGreaterS16, a, b);
case 32:
return Inst<U128>(Opcode::VectorGreaterS32, a, b);
case 64:
return Inst<U128>(Opcode::VectorGreaterS64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorInterleaveLower(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:

1
src/frontend/ir/ir_emitter.h
View file

@ -215,6 +215,7 @@ public:
U128 VectorBroadcastLower(size_t esize, const UAny& a);
U128 VectorEor(const U128& a, const U128& b);
U128 VectorEqual(size_t esize, const U128& a, const U128& b);
U128 VectorGreaterSigned(size_t esize, const U128& a, const U128& b);
U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b);
U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount);
U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount);

4
src/frontend/ir/opcodes.inc
View file

@ -226,6 +226,10 @@ OPCODE(VectorEqual16, T::U128, T::U128, T::U128
OPCODE(VectorEqual32, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual64, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual128, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS8, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS16, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS32, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS64, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower8, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower16, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower32, T::U128, T::U128, T::U128 )