thumb32: Implement EOR (immediate)
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3 changed files with 20 additions and 1 deletions
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@ -61,7 +61,7 @@ INST(thumb32_ORR_imm, "ORR (imm)", "11110v00010Snnnn0vvvdd
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INST(thumb32_MVN_imm, "MVN (imm)", "11110v00011S11110vvvddddvvvvvvvv")
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INST(thumb32_ORN_imm, "ORN (imm)", "11110v00011Snnnn0vvvddddvvvvvvvv")
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INST(thumb32_TEQ_imm, "TEQ (imm)", "11110v001001nnnn0vvv1111vvvvvvvv")
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//INST(thumb32_EOR_imm, "EOR (imm)", "11110-00100-----0---------------")
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INST(thumb32_EOR_imm, "EOR (imm)", "11110v00100Snnnn0vvvddddvvvvvvvv")
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//INST(thumb32_CMN_imm, "CMN (imm)", "11110-010001----0---1111--------")
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//INST(thumb32_ADD_imm_1, "ADD (imm)", "11110-01000-----0---------------")
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//INST(thumb32_ADC_imm, "ADC (imm)", "11110-01010-----0---------------")
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@ -140,4 +140,22 @@ bool ThumbTranslatorVisitor::thumb32_TEQ_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
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ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
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if ((d == Reg::PC && !S) || n == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto imm_carry = ThumbExpandImm_C(i, imm3, imm8, ir.GetCFlag());
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const auto result = ir.Eor(ir.GetRegister(n), ir.Imm32(imm_carry.imm32));
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(imm_carry.carry);
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}
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return true;
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}
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} // namespace Dynarmic::A32
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@ -157,6 +157,7 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_MVN_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Imm<8> imm8);
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bool thumb32_ORN_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
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bool thumb32_TEQ_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);
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bool thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
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// thumb32 miscellaneous control instructions
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bool thumb32_UDF();
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