IR: Remove VectorShuffleWords
Introduce VectorRotateWholeVectorRight
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8fb37e0e4f
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f92cb5e66f
9 changed files with 41 additions and 40 deletions
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@ -1321,6 +1321,15 @@ void EmitIR<IR::Opcode::VectorReduceAdd64>(oaknut::CodeGenerator& code, EmitCont
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EmitReduce<64>(code, ctx, inst, [&](auto& Dresult, auto Voperand) { code.ADDP(Dresult, Voperand); });
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}
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template<>
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void EmitIR<IR::Opcode::VectorRotateWholeVectorRight>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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EmitImmShift<8>(code, ctx, inst, [&](auto Vresult, auto Voperand, u8 shift_amount) {
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ASSERT(shift_amount % 8 == 0);
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const u8 ext_imm = (shift_amount % 128) / 8;
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code.EXT(Vresult, Voperand, Voperand, ext_imm);
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});
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}
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template<>
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void EmitIR<IR::Opcode::VectorRoundingHalvingAddS8>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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EmitThreeOpArranged<8>(code, ctx, inst, [&](auto Vresult, auto Va, auto Vb) { code.SRHADD(Vresult, Va, Vb); });
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@ -1391,14 +1400,6 @@ void EmitIR<IR::Opcode::VectorRoundingShiftLeftU64>(oaknut::CodeGenerator& code,
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EmitThreeOpArranged<64>(code, ctx, inst, [&](auto Vresult, auto Va, auto Vb) { code.URSHL(Vresult, Va, Vb); });
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}
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template<>
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void EmitIR<IR::Opcode::VectorShuffleWords>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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(void)code;
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(void)ctx;
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(void)inst;
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ASSERT_FALSE("Unimplemented");
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}
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template<>
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void EmitIR<IR::Opcode::VectorSignExtend8>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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EmitTwoOpArrangedWiden<8>(code, ctx, inst, [&](auto Vresult, auto Voperand) { code.SXTL(Vresult, Voperand); });
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@ -4,6 +4,7 @@
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*/
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#include <algorithm>
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#include <bit>
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#include <bitset>
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#include <cstdlib>
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#include <type_traits>
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@ -3320,6 +3321,20 @@ void EmitX64::EmitVectorReduceAdd64(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, data);
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}
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void EmitX64::EmitVectorRotateWholeVectorRight(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm operand = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const u8 shift_amount = args[1].GetImmediateU8();
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ASSERT(shift_amount % 32 == 0);
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const u8 shuffle_imm = std::rotr<u8>(0b11100100, shift_amount / 32 * 2);
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code.pshufd(result, operand, shuffle_imm);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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static void EmitVectorRoundingHalvingAddSigned(size_t esize, EmitContext& ctx, IR::Inst* inst, BlockOfCode& code) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -3501,22 +3516,6 @@ void EmitX64::EmitVectorRoundingShiftLeftU64(EmitContext& ctx, IR::Inst* inst) {
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});
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}
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static void VectorShuffleImpl(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, void (Xbyak::CodeGenerator::*fn)(const Xbyak::Mmx&, const Xbyak::Operand&, u8)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm operand = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const u8 mask = args[1].GetImmediateU8();
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(code.*fn)(result, operand, mask);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitVectorShuffleWords(EmitContext& ctx, IR::Inst* inst) {
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VectorShuffleImpl(code, ctx, inst, &Xbyak::CodeGenerator::pshufd);
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}
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void EmitX64::EmitVectorSignExtend8(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.HasHostFeature(HostFeature::SSE41)) {
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@ -103,7 +103,7 @@ bool TranslatorVisitor::ZIP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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// TODO: Urgh.
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const IR::U128 interleaved = ir.VectorInterleaveLower(esize, operand1, operand2);
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return ir.VectorZeroUpper(ir.VectorShuffleWords(interleaved, 0b01001110));
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return ir.VectorZeroUpper(ir.VectorRotateWholeVectorRight(interleaved, 64));
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}();
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V(datasize, Vd, result);
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@ -39,7 +39,7 @@ IR::U128 SHA1HashUpdate(IREmitter& ir, Vec Vm, Vec Vn, Vec Vd, SHA1HashUpdateFun
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// Move each 32-bit element to the left once
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// e.g. [3, 2, 1, 0], becomes [2, 1, 0, 3]
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const IR::U128 shuffled_x = ir.VectorShuffleWords(x, 0b10010011);
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const IR::U128 shuffled_x = ir.VectorRotateWholeVectorRight(x, 96);
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x = ir.VectorSetElement(32, shuffled_x, 0, y);
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y = high_x;
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}
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@ -91,7 +91,7 @@ bool TranslatorVisitor::SHA1SU1(Vec Vn, Vec Vd) {
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const IR::U128 n = ir.GetQ(Vn);
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// Shuffle down the whole vector and zero out the top 32 bits
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const IR::U128 shuffled_n = ir.VectorSetElement(32, ir.VectorShuffleWords(n, 0b00111001), 3, ir.Imm32(0));
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const IR::U128 shuffled_n = ir.VectorSetElement(32, ir.VectorRotateWholeVectorRight(n, 32), 3, ir.Imm32(0));
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const IR::U128 t = ir.VectorEor(d, shuffled_n);
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const IR::U128 rotated_t = ir.VectorRotateLeft(32, t, 1);
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@ -141,7 +141,7 @@ IR::U128 SM4Hash(IREmitter& ir, Vec Vn, Vec Vd, SM4RotationType type) {
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const IR::U32 intval_low_word = ir.VectorGetElement(32, intval_vec, 0);
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const IR::U32 round_result_low_word = ir.VectorGetElement(32, roundresult, 0);
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const IR::U32 intval = SM4Rotation(ir, intval_low_word, round_result_low_word, type);
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roundresult = ir.VectorShuffleWords(roundresult, 0b00111001);
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roundresult = ir.VectorRotateWholeVectorRight(roundresult, 32);
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roundresult = ir.VectorSetElement(32, roundresult, 3, intval);
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}
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@ -235,7 +235,7 @@ bool TranslatorVisitor::SM3PARTW1(Vec Vm, Vec Vn, Vec Vd) {
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const IR::U128 result_low_three_words = [&] {
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// Move the top-most 3 words down one element (i.e. [3, 2, 1, 0] -> [0, 3, 2, 1])
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const IR::U128 shuffled_m = ir.VectorShuffleWords(m, 0b00111001);
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const IR::U128 shuffled_m = ir.VectorRotateWholeVectorRight(m, 32);
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// We treat the uppermost word as junk data and don't touch/use it explicitly for now.
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// Given we don't do anything with it yet, the fact we EOR into it doesn't matter.
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@ -1695,6 +1695,11 @@ U128 IREmitter::VectorRotateRight(size_t esize, const U128& a, u8 amount) {
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VectorLogicalShiftLeft(esize, a, static_cast<u8>(esize - amount)));
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}
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U128 IREmitter::VectorRotateWholeVectorRight(const U128& a, u8 amount) {
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ASSERT(amount % 32 == 0);
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return Inst<U128>(Opcode::VectorRotateWholeVectorRight, a, Imm8(amount));
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}
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U128 IREmitter::VectorRoundingHalvingAddSigned(size_t esize, const U128& a, const U128& b) {
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switch (esize) {
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case 8:
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@ -1751,10 +1756,6 @@ U128 IREmitter::VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, con
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UNREACHABLE();
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}
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U128 IREmitter::VectorShuffleWords(const U128& a, u8 mask) {
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return Inst<U128>(Opcode::VectorShuffleWords, a, mask);
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}
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U128 IREmitter::VectorSignExtend(size_t original_esize, const U128& a) {
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switch (original_esize) {
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case 8:
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@ -291,11 +291,11 @@ public:
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U128 VectorReduceAdd(size_t esize, const U128& a);
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U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount);
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U128 VectorRotateRight(size_t esize, const U128& a, u8 amount);
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U128 VectorRotateWholeVectorRight(const U128& a, u8 amount);
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U128 VectorRoundingHalvingAddSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b);
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U128 VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b);
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U128 VectorShuffleWords(const U128& a, u8 mask);
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U128 VectorSignExtend(size_t original_esize, const U128& a);
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U128 VectorSignedAbsoluteDifference(size_t esize, const U128& a, const U128& b);
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UpperAndLower VectorSignedMultiply(size_t esize, const U128& a, const U128& b);
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@ -465,6 +465,7 @@ OPCODE(VectorReduceAdd8, U128, U128
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OPCODE(VectorReduceAdd16, U128, U128 )
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OPCODE(VectorReduceAdd32, U128, U128 )
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OPCODE(VectorReduceAdd64, U128, U128 )
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OPCODE(VectorRotateWholeVectorRight, U128, U128, U8 )
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OPCODE(VectorRoundingHalvingAddS8, U128, U128, U128 )
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OPCODE(VectorRoundingHalvingAddS16, U128, U128, U128 )
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OPCODE(VectorRoundingHalvingAddS32, U128, U128, U128 )
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@ -479,7 +480,6 @@ OPCODE(VectorRoundingShiftLeftU8, U128, U128
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OPCODE(VectorRoundingShiftLeftU16, U128, U128, U128 )
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OPCODE(VectorRoundingShiftLeftU32, U128, U128, U128 )
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OPCODE(VectorRoundingShiftLeftU64, U128, U128, U128 )
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OPCODE(VectorShuffleWords, U128, U128, U8 )
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OPCODE(VectorSignExtend8, U128, U128 )
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OPCODE(VectorSignExtend16, U128, U128 )
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OPCODE(VectorSignExtend32, U128, U128 )
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@ -45,7 +45,7 @@ void PolyfillSHA256MessageSchedule1(IR::IREmitter& ir, IR::Inst& inst) {
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const IR::U128 T0 = ir.VectorExtract(y, z, 32);
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const IR::U128 lower_half = [&] {
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const IR::U128 T = ir.VectorShuffleWords(z, 0b01001110);
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const IR::U128 T = ir.VectorRotateWholeVectorRight(z, 64);
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const IR::U128 tmp1 = ir.VectorRotateRight(32, T, 17);
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const IR::U128 tmp2 = ir.VectorRotateRight(32, T, 19);
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const IR::U128 tmp3 = ir.VectorLogicalShiftRight(32, T, 10);
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@ -61,8 +61,8 @@ void PolyfillSHA256MessageSchedule1(IR::IREmitter& ir, IR::Inst& inst) {
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const IR::U128 tmp4 = ir.VectorEor(tmp1, ir.VectorEor(tmp2, tmp3));
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// Shuffle the top two 32-bit elements downwards [3, 2, 1, 0] -> [1, 0, 3, 2]
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const IR::U128 shuffled_d = ir.VectorShuffleWords(x, 0b01001110);
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const IR::U128 shuffled_T0 = ir.VectorShuffleWords(T0, 0b01001110);
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const IR::U128 shuffled_d = ir.VectorRotateWholeVectorRight(x, 64);
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const IR::U128 shuffled_T0 = ir.VectorRotateWholeVectorRight(T0, 64);
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const IR::U128 tmp5 = ir.VectorAdd(32, tmp4, ir.VectorAdd(32, shuffled_d, shuffled_T0));
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return ir.VectorGetElement(64, tmp5, 0);
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@ -128,8 +128,8 @@ void PolyfillSHA256Hash(IR::IREmitter& ir, IR::Inst& inst) {
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const IR::U32 new_low_y = ir.Add(t, high_x);
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// Shuffle all words left by 1 element: [3, 2, 1, 0] -> [2, 1, 0, 3]
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const IR::U128 shuffled_x = ir.VectorShuffleWords(x, 0b10010011);
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const IR::U128 shuffled_y = ir.VectorShuffleWords(y, 0b10010011);
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const IR::U128 shuffled_x = ir.VectorRotateWholeVectorRight(x, 96);
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const IR::U128 shuffled_y = ir.VectorRotateWholeVectorRight(y, 96);
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x = ir.VectorSetElement(32, shuffled_x, 0, new_low_x);
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y = ir.VectorSetElement(32, shuffled_y, 0, new_low_y);
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