IR: Implement FPVectorMulX

This commit is contained in:
MerryMage 2018-11-17 21:31:22 +00:00
parent bbd8abaa25
commit fa8925c4df
4 changed files with 58 additions and 0 deletions

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@ -954,6 +954,50 @@ void EmitX64::EmitFPVectorMulAdd64(EmitContext& ctx, IR::Inst* inst) {
EmitFPVectorMulAdd<64>(code, ctx, inst);
}
template<size_t fsize>
static void EmitFPVectorMulX(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
using FPT = mp::unsigned_integer_of_size<fsize>;
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseXmm(args[0]);
const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(args[1]);
const Xbyak::Xmm nan_mask = ctx.reg_alloc.ScratchXmm();
code.movaps(nan_mask, xmm_b);
code.movaps(result, xmm_a);
FCODE(cmpunordp)(nan_mask, xmm_a);
FCODE(mulp)(result, xmm_b);
FCODE(cmpunordp)(nan_mask, result);
const auto nan_handler = static_cast<void(*)(std::array<VectorArray<FPT>, 3>&, FP::FPCR)>(
[](std::array<VectorArray<FPT>, 3>& values, FP::FPCR fpcr) {
VectorArray<FPT>& result = values[0];
for (size_t elementi = 0; elementi < result.size(); ++elementi) {
if (auto r = FP::ProcessNaNs(values[1][elementi], values[2][elementi])) {
result[elementi] = fpcr.DN() ? FP::FPInfo<FPT>::DefaultNaN() : *r;
} else if (FP::IsNaN(result[elementi])) {
const FPT sign = (values[1][elementi] ^ values[2][elementi]) & FP::FPInfo<FPT>::sign_mask;
result[elementi] = sign | FP::FPValue<FPT, false, 0, 2>();
}
}
}
);
HandleNaNs<fsize, 2>(code, ctx, {result, xmm_a, xmm_b}, nan_mask, nan_handler);
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitX64::EmitFPVectorMulX32(EmitContext& ctx, IR::Inst* inst) {
EmitFPVectorMulX<32>(code, ctx, inst);
}
void EmitX64::EmitFPVectorMulX64(EmitContext& ctx, IR::Inst* inst) {
EmitFPVectorMulX<64>(code, ctx, inst);
}
void EmitX64::EmitFPVectorNeg16(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

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@ -2135,6 +2135,17 @@ U128 IREmitter::FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const
return {};
}
U128 IREmitter::FPVectorMulX(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorMulX32, a, b);
case 64:
return Inst<U128>(Opcode::FPVectorMulX64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorNeg(size_t esize, const U128& a) {
switch (esize) {
case 16:

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@ -334,6 +334,7 @@ public:
U128 FPVectorMin(size_t esize, const U128& a, const U128& b);
U128 FPVectorMul(size_t esize, const U128& a, const U128& b);
U128 FPVectorMulAdd(size_t esize, const U128& addend, const U128& op1, const U128& op2);
U128 FPVectorMulX(size_t esize, const U128& a, const U128& b);
U128 FPVectorNeg(size_t esize, const U128& a);
U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b);

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@ -543,6 +543,8 @@ OPCODE(FPVectorMul32, U128, U128
OPCODE(FPVectorMul64, U128, U128, U128 )
OPCODE(FPVectorMulAdd32, U128, U128, U128, U128 )
OPCODE(FPVectorMulAdd64, U128, U128, U128, U128 )
OPCODE(FPVectorMulX32, U128, U128, U128 )
OPCODE(FPVectorMulX64, U128, U128, U128 )
OPCODE(FPVectorNeg16, U128, U128 )
OPCODE(FPVectorNeg32, U128, U128 )
OPCODE(FPVectorNeg64, U128, U128 )