A32: Implement ARM-mode BFC

src/frontend/A32/decoder/arm.inc

@@ -164,6 +164,7 @@ INST(arm_STMIB,         "STMIB",               "cccc100110w0nnnnxxxxxxxxxxxxxxxx
 INST(arm_STM_usr,       "STM (usr reg)",       "----100--100--------------------") // all
 
 // Miscellaneous instructions
+INST(arm_BFC,           "BFC",                 "cccc0111110vvvvvddddvvvvv0011111") // v6T2
 INST(arm_CLZ,           "CLZ",                 "cccc000101101111dddd11110001mmmm") // v5
 INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
 INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6

src/frontend/A32/disassembler/disassembler_arm.cpp

@@ -583,6 +583,9 @@ public:
     std::string arm_STM_usr() { return "ice"; }
 
     // Miscellaneous instructions
+    std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
+        return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1);
+    }
     std::string arm_CLZ(Cond cond, Reg d, Reg m) {
         return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
     }

src/frontend/A32/translate/translate_arm/misc.cpp

@@ -4,10 +4,32 @@
  * General Public License version 2 or any later version.
  */
 
+#include "common/bit_util.h"
 #include "translate_arm.h"
 
 namespace Dynarmic::A32 {
 
+// BFC<c> <Rd>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
+    if (d == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+    if (msb < lsb) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const u32 mask = ~(Common::Ones<u32>(msb - lsb + 1) << lsb);
+    const IR::U32 operand = ir.GetRegister(d);
+    const IR::U32 result = ir.And(operand, ir.Imm32(mask));
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // CLZ<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
     if (d == Reg::PC || m == Reg::PC) {

src/frontend/A32/translate/translate_arm/translate_arm.h

@@ -207,6 +207,7 @@ struct ArmTranslatorVisitor final {
     bool arm_STM_usr();
 
     // Miscellaneous instructions
+    bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
     bool arm_CLZ(Cond cond, Reg d, Reg m);
     bool arm_NOP() { return true; }
     bool arm_RBIT(Cond cond, Reg d, Reg m);

tests/A32/fuzz_arm.cpp

@@ -1080,19 +1080,29 @@ TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][.vfp][A32]") {
 }
 
 TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
-    const auto is_clz_valid = [](u32 instr) -> bool {
+    const auto is_bfc_valid = [](u32 instr) {
+        if (Bits<12, 15>(instr) == 0b1111) {
+            // Destination register may not be the PC.
+            return false;
+        }
+        // msb must be greater than or equal to the lsb,
+        // otherwise the instruction is UNPREDICTABLE.
+        return Bits<16, 20>(instr) >= Bits<7, 11>(instr);
+    };
+    const auto is_clz_valid = [](u32 instr) {
         // R15 as Rd, or Rm is UNPREDICTABLE
         return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111;
     };
 
-    const InstructionGenerator clz_instr = InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid); // CLZ
+    const std::array instructions = {
+        InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_valid), // BFC
+        InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ
+    };
 
-    SECTION("Fuzz CLZ") {
+    FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {
-        FuzzJitArm(1, 1, 1000, [&clz_instr]() -> u32 {
+        return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
-            return clz_instr.Generate();
     });
 }
-}
 
 TEST_CASE("Test ARM MSR instructions", "[JitX64][A32]") {
     const auto is_msr_valid = [](u32 instr) -> bool {