Merge pull request #442 from lioncash/fcvtxn

A64: Implement scalar and vector variants of FCVTXN

src/CMakeLists.txt

@@ -24,6 +24,8 @@ add_library(dynarmic
     common/fp/info.h
     common/fp/mantissa_util.h
     common/fp/op.h
+    common/fp/op/FPConvert.cpp
+    common/fp/op/FPConvert.h
     common/fp/op/FPMulAdd.cpp
     common/fp/op/FPMulAdd.h
     common/fp/op/FPRecipEstimate.cpp

src/backend/x64/emit_x64_floating_point.cpp

@@ -1034,26 +1034,46 @@ void EmitX64::EmitFPCompare64(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitFPSingleToDouble(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
+    const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
 
-    code.cvtss2sd(result, result);
+    // We special-case the non-IEEE-defined ToOdd rounding mode.
-    if (ctx.FPSCR_DN()) {
+    if (rounding_mode == ctx.FPSCR_RMode() && rounding_mode != FP::RoundingMode::ToOdd) {
-        ForceToDefaultNaN<64>(code, result);
+        const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
+
+        code.cvtss2sd(result, result);
+        if (ctx.FPSCR_DN()) {
+            ForceToDefaultNaN<64>(code, result);
+        }
+        ctx.reg_alloc.DefineValue(inst, result);
+    } else {
+        ctx.reg_alloc.HostCall(inst, args[0]);
+        code.mov(code.ABI_PARAM2.cvt32(), ctx.FPCR());
+        code.mov(code.ABI_PARAM3.cvt32(), static_cast<u32>(rounding_mode));
+        code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]);
+        code.CallFunction(&FP::FPConvert<u64, u32>);
     }
-
-    ctx.reg_alloc.DefineValue(inst, result);
 }
 
 void EmitX64::EmitFPDoubleToSingle(EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
+    const auto rounding_mode = static_cast<FP::RoundingMode>(args[1].GetImmediateU8());
 
-    code.cvtsd2ss(result, result);
+    // We special-case the non-IEEE-defined ToOdd rounding mode.
-    if (ctx.FPSCR_DN()) {
+    if (rounding_mode == ctx.FPSCR_RMode() && rounding_mode != FP::RoundingMode::ToOdd) {
-        ForceToDefaultNaN<32>(code, result);
+        const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
+
+        code.cvtsd2ss(result, result);
+        if (ctx.FPSCR_DN()) {
+            ForceToDefaultNaN<32>(code, result);
+        }
+        ctx.reg_alloc.DefineValue(inst, result);
+    } else {
+        ctx.reg_alloc.HostCall(inst, args[0]);
+        code.mov(code.ABI_PARAM2.cvt32(), ctx.FPCR());
+        code.mov(code.ABI_PARAM3.cvt32(), static_cast<u32>(rounding_mode));
+        code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]);
+        code.CallFunction(&FP::FPConvert<u32, u64>);
     }
-
-    ctx.reg_alloc.DefineValue(inst, result);
 }
 
 template<size_t fsize, bool unsigned_, size_t isize>

src/common/fp/op.h

@@ -6,6 +6,7 @@
 
 #pragma once
 
+#include "common/fp/op/FPConvert.h"
 #include "common/fp/op/FPMulAdd.h"
 #include "common/fp/op/FPRecipEstimate.h"
 #include "common/fp/op/FPRecipExponent.h"

src/common/fp/op/FPConvert.cpp

@@ -0,0 +1,102 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2019 MerryMage
+ * This software may be used and distributed according to the terms of the GNU
+ * General Public License version 2 or any later version.
+ */
+
+#include <tuple>
+
+#include "common/common_types.h"
+#include "common/fp/fpcr.h"
+#include "common/fp/fpsr.h"
+#include "common/fp/info.h"
+#include "common/fp/op/FPRecipEstimate.h"
+#include "common/fp/process_exception.h"
+#include "common/fp/process_nan.h"
+#include "common/fp/unpacked.h"
+
+namespace Dynarmic::FP {
+namespace {
+// We don't care about unreachable code warnings here
+// TODO: Remove this disabling of warnings when
+// half-float support is added.
+#ifdef _MSC_VER
+#pragma warning(disable:4702)
+#endif
+template <typename FPT_TO, typename FPT_FROM>
+FPT_TO FPConvertNaN(FPT_FROM op) {
+    const bool sign = Common::Bit<Common::BitSize<FPT_FROM>() - 1>(op);
+    const u64 frac = [op] {
+        if constexpr (sizeof(FPT_FROM) == sizeof(u64)) {
+            return Common::Bits<0, 50>(op);
+        }
+
+        if constexpr (sizeof(FPT_FROM) == sizeof(u32)) {
+            return u64{Common::Bits<0, 21>(op)} << 29;
+        }
+
+        return u64{Common::Bits<0, 8>(op)} << 42;
+    }();
+
+    const size_t dest_bit_size = Common::BitSize<FPT_TO>();
+    const u64 shifted_sign = u64{sign} << (dest_bit_size - 1);
+    const u64 exponent = Common::Ones<u64>(dest_bit_size - FPInfo<FPT_TO>::explicit_mantissa_width);
+
+    if constexpr (sizeof(FPT_TO) == sizeof(u64)) {
+        return FPT_TO(shifted_sign | exponent << 52 | frac);
+    }
+
+    if constexpr (sizeof(FPT_TO) == sizeof(u32)) {
+        return FPT_TO(shifted_sign | exponent << 22 | Common::Bits<29, 50>(frac));
+    }
+
+    return FPT_TO(shifted_sign | exponent << 9 | Common::Bits<42, 50>(frac));
+}
+#ifdef _MSC_VER
+#pragma warning(default:4702)
+#endif
+} // Anonymous namespace
+
+template <typename FPT_TO, typename FPT_FROM>
+FPT_TO FPConvert(FPT_FROM op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr) {
+    const auto [type, sign, value] = FPUnpack<FPT_FROM>(op, fpcr, fpsr);
+    const bool is_althp = Common::BitSize<FPT_TO>() == 16 && fpcr.AHP();
+
+    if (type == FPType::SNaN || type == FPType::QNaN) {
+        FPT_TO result{};
+
+        if (is_althp) {
+            result = FPInfo<FPT_TO>::Zero(sign);
+        } else if (fpcr.DN()) {
+            result = FPInfo<FPT_TO>::DefaultNaN();
+        } else {
+            result = FPConvertNaN<FPT_TO>(op);
+        }
+
+        if (type == FPType::SNaN || is_althp) {
+            FPProcessException(FPExc::InvalidOp, fpcr, fpsr);
+        }
+
+        return result;
+    }
+
+    if (type == FPType::Infinity) {
+        if (is_althp) {
+            FPProcessException(FPExc::InvalidOp, fpcr, fpsr);
+            return static_cast<FPT_TO>(u32{sign} << 15 | 0b111111111111111);
+        }
+
+        return FPInfo<FPT_TO>::Infinity(sign);
+    }
+
+    if (type == FPType::Zero) {
+        return FPInfo<FPT_TO>::Zero(sign);
+    }
+
+    return FPRoundBase<FPT_TO>(value, fpcr, rounding_mode, fpsr);
+}
+
+template u64 FPConvert<u64, u32>(u32 op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr);
+template u32 FPConvert<u32, u64>(u64 op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr);
+
+} // namespace Dynarmic::FP

src/common/fp/op/FPConvert.h

@@ -0,0 +1,18 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2019 MerryMage
+ * This software may be used and distributed according to the terms of the GNU
+ * General Public License version 2 or any later version.
+ */
+
+#pragma once
+
+namespace Dynarmic::FP {
+
+class FPCR;
+class FPSR;
+enum class RoundingMode;
+
+template <typename FPT_TO, typename FPT_FROM>
+FPT_TO FPConvert(FPT_FROM op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr);
+
+} // namespace Dynarmic::FP

src/frontend/A32/translate/translate_arm/vfp2.cpp

@@ -479,12 +479,13 @@ bool ArmTranslatorVisitor::vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool s
     const auto d = ToExtReg(!sz, Vd, D); // Destination is of opposite size to source
     const auto m = ToExtReg(sz, Vm, M);
     const auto reg_m = ir.GetExtendedRegister(m);
+    const auto rounding_mode = ir.current_location.FPSCR().RMode();
 
     if (sz) {
-        const auto result = ir.FPDoubleToSingle(reg_m, true);
+        const auto result = ir.FPDoubleToSingle(reg_m, rounding_mode);
         ir.SetExtendedRegister(d, result);
     } else {
-        const auto result = ir.FPSingleToDouble(reg_m, true);
+        const auto result = ir.FPSingleToDouble(reg_m, rounding_mode);
         ir.SetExtendedRegister(d, result);
     }
 

src/frontend/A64/decoder/a64.inc

@@ -462,7 +462,7 @@ INST(CMLE_1,                 "CMLE (zero)",                               "01111
 INST(NEG_1,                  "NEG (vector)",                              "01111110zz100000101110nnnnnddddd")
 INST(SQXTUN_1,               "SQXTUN, SQXTUN2",                           "01111110zz100001001010nnnnnddddd")
 INST(UQXTN_1,                "UQXTN, UQXTN2",                             "01111110zz100001010010nnnnnddddd")
-//INST(FCVTXN_1,               "FCVTXN, FCVTXN2",                           "011111100z100001011010nnnnnddddd")
+INST(FCVTXN_1,               "FCVTXN, FCVTXN2",                           "011111100z100001011010nnnnnddddd")
 
 // Data Processing - FP and SIMD - SIMD Scalar pairwise
 INST(ADDP_pair,              "ADDP (scalar)",                             "01011110zz110001101110nnnnnddddd")
@@ -664,7 +664,7 @@ INST(NEG_2,                  "NEG (vector)",                              "0Q101
 INST(SQXTUN_2,               "SQXTUN, SQXTUN2",                           "0Q101110zz100001001010nnnnnddddd")
 INST(SHLL,                   "SHLL, SHLL2",                               "0Q101110zz100001001110nnnnnddddd")
 INST(UQXTN_2,                "UQXTN, UQXTN2",                             "0Q101110zz100001010010nnnnnddddd")
-//INST(FCVTXN_2,               "FCVTXN, FCVTXN2",                           "0Q1011100z100001011010nnnnnddddd")
+INST(FCVTXN_2,               "FCVTXN, FCVTXN2",                           "0Q1011100z100001011010nnnnnddddd")
 //INST(FRINTA_1,               "FRINTA (vector)",                           "0Q10111001111001100010nnnnnddddd")
 INST(FRINTA_2,               "FRINTA (vector)",                           "0Q1011100z100001100010nnnnnddddd")
 //INST(FRINTX_1,               "FRINTX (vector)",                           "0Q10111001111001100110nnnnnddddd")

src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp

@@ -104,7 +104,9 @@ bool TranslatorVisitor::FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd) {
         return UnallocatedEncoding();
     }
 
-    IR::UAny operand = V_scalar(*srcsize, Vn);
+    const IR::UAny operand = V_scalar(*srcsize, Vn);
+    const auto rounding_mode = ir.current_location->FPCR().RMode();
+
     IR::UAny result;
     switch (*srcsize) {
     case 16:
@@ -120,7 +122,7 @@ bool TranslatorVisitor::FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd) {
         case 16:
             return InterpretThisInstruction();
         case 64:
-            result = ir.FPSingleToDouble(operand, true);
+            result = ir.FPSingleToDouble(operand, rounding_mode);
             break;
         }
         break;
@@ -129,7 +131,7 @@ bool TranslatorVisitor::FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd) {
         case 16:
             return InterpretThisInstruction();
         case 32:
-            result = ir.FPDoubleToSingle(operand, true);
+            result = ir.FPDoubleToSingle(operand, rounding_mode);
             break;
         }
         break;

src/frontend/A64/translate/impl/impl.h

@@ -746,7 +746,7 @@ struct TranslatorVisitor final {
     bool NEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
     bool SQXTUN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
     bool UQXTN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
-    bool FCVTXN_2(bool Q, bool sz, Vec Vn, Reg Rd);
+    bool FCVTXN_2(bool Q, bool sz, Vec Vn, Vec Vd);
     bool FRINTN_1(bool Q, Vec Vn, Vec Vd);
     bool FRINTN_2(bool Q, bool sz, Vec Vn, Vec Vd);
     bool FRINTM_1(bool Q, Vec Vn, Vec Vd);

src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp

@@ -152,6 +152,18 @@ bool TranslatorVisitor::FCVTPU_2(bool sz, Vec Vn, Vec Vd) {
     return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, Signedness::Unsigned);
 }
 
+bool TranslatorVisitor::FCVTXN_1(bool sz, Vec Vn, Vec Vd) {
+    if (!sz) {
+        return UnallocatedEncoding();
+    }
+
+    const IR::U64 element = V_scalar(64, Vn);
+    const IR::U32 result = ir.FPDoubleToSingle(element, FP::RoundingMode::ToOdd);
+
+    V_scalar(32, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::FCVTZS_int_2(bool sz, Vec Vn, Vec Vd) {
     return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Signed);
 }

src/frontend/A64/translate/impl/simd_two_register_misc.cpp

@@ -348,10 +348,11 @@ bool TranslatorVisitor::FCVTL(bool Q, bool sz, Vec Vn, Vec Vd) {
     }
 
     const IR::U128 part = Vpart(64, Vn, Q);
+    const auto rounding_mode = ir.current_location->FPCR().RMode();
     IR::U128 result = ir.ZeroVector();
 
     for (size_t i = 0; i < 2; i++) {
-        const IR::U64 element = ir.FPSingleToDouble(ir.VectorGetElement(32, part, i), true);
+        const IR::U64 element = ir.FPSingleToDouble(ir.VectorGetElement(32, part, i), rounding_mode);
 
         result = ir.VectorSetElement(64, result, i, element);
     }
@@ -367,10 +368,11 @@ bool TranslatorVisitor::FCVTN(bool Q, bool sz, Vec Vn, Vec Vd) {
     }
 
     const IR::U128 operand = V(128, Vn);
+    const auto rounding_mode = ir.current_location->FPCR().RMode();
     IR::U128 result = ir.ZeroVector();
 
     for (size_t i = 0; i < 2; i++) {
-        const IR::U32 element = ir.FPDoubleToSingle(ir.VectorGetElement(64, operand, i), true);
+        const IR::U32 element = ir.FPDoubleToSingle(ir.VectorGetElement(64, operand, i), rounding_mode);
 
         result = ir.VectorSetElement(32, result, i, element);
     }
@@ -395,6 +397,26 @@ bool TranslatorVisitor::FCVTPS_4(bool Q, bool sz, Vec Vn, Vec Vd) {
     return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::TowardsPlusInfinity);
 }
 
+bool TranslatorVisitor::FCVTXN_2(bool Q, bool sz, Vec Vn, Vec Vd) {
+    if (!sz) {
+        return UnallocatedEncoding();
+    }
+
+    const size_t part = Q ? 1 : 0;
+    const auto operand = ir.GetQ(Vn);
+    auto result = ir.ZeroVector();
+
+    for (size_t e = 0; e < 2; ++e) {
+        const IR::U64 element = ir.VectorGetElement(64, operand, e);
+        const IR::U32 converted = ir.FPDoubleToSingle(element, FP::RoundingMode::ToOdd);
+
+        result = ir.VectorSetElement(32, result, e, converted);
+    }
+
+    Vpart(64, Vd, part, result);
+    return true;
+}
+
 bool TranslatorVisitor::FCVTZS_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
     return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::TowardsZero);
 }

src/frontend/ir/ir_emitter.cpp

@@ -1948,14 +1948,12 @@ U32U64 IREmitter::FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled)
     }
 }
 
-U32 IREmitter::FPDoubleToSingle(const U64& a, bool fpcr_controlled) {
+U32 IREmitter::FPDoubleToSingle(const U64& a, FP::RoundingMode rounding) {
-    ASSERT(fpcr_controlled);
+    return Inst<U32>(Opcode::FPDoubleToSingle, a, Imm8(static_cast<u8>(rounding)));
-    return Inst<U32>(Opcode::FPDoubleToSingle, a);
 }
 
-U64 IREmitter::FPSingleToDouble(const U32& a, bool fpcr_controlled) {
+U64 IREmitter::FPSingleToDouble(const U32& a, FP::RoundingMode rounding) {
-    ASSERT(fpcr_controlled);
+    return Inst<U64>(Opcode::FPSingleToDouble, a, Imm8(static_cast<u8>(rounding)));
-    return Inst<U64>(Opcode::FPSingleToDouble, a);
 }
 
 U32 IREmitter::FPToFixedS32(const U32U64& a, size_t fbits, FP::RoundingMode rounding) {

src/frontend/ir/ir_emitter.h

@@ -312,8 +312,8 @@ public:
     U32U64 FPRSqrtStepFused(const U32U64& a, const U32U64& b);
     U32U64 FPSqrt(const U32U64& a);
     U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled);
-    U32 FPDoubleToSingle(const U64& a, bool fpcr_controlled);
+    U32 FPDoubleToSingle(const U64& a, FP::RoundingMode rounding);
-    U64 FPSingleToDouble(const U32& a, bool fpcr_controlled);
+    U64 FPSingleToDouble(const U32& a, FP::RoundingMode rounding);
     U32 FPToFixedS32(const U32U64& a, size_t fbits, FP::RoundingMode rounding);
     U64 FPToFixedS64(const U32U64& a, size_t fbits, FP::RoundingMode rounding);
     U32 FPToFixedU32(const U32U64& a, size_t fbits, FP::RoundingMode rounding);

src/frontend/ir/opcodes.inc

@@ -500,8 +500,8 @@ OPCODE(FPSub32,                                             U32,            U32,
 OPCODE(FPSub64,                                             U64,            U64,            U64                                             )
 
 // Floating-point conversions
-OPCODE(FPSingleToDouble,                                    U64,            U32                                                             )
+OPCODE(FPSingleToDouble,                                    U64,            U32,            U8                                              )
-OPCODE(FPDoubleToSingle,                                    U32,            U64                                                             )
+OPCODE(FPDoubleToSingle,                                    U32,            U64,            U8                                              )
 OPCODE(FPDoubleToFixedS32,                                  U32,            U64,            U8,             U8                              )
 OPCODE(FPDoubleToFixedS64,                                  U64,            U64,            U8,             U8                              )
 OPCODE(FPDoubleToFixedU32,                                  U32,            U64,            U8,             U8                              )