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A64: Implement SIMD instruction USHR, vector variant

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This commit is contained in:
MerryMage 2018-02-10 11:05:58 +00:00
parent b22c5961f9
commit fb9d20f27f
2 changed files with 20 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -791,7 +791,7 @@ INST(SHL_2, "SHL", "0Q001
//INST(SSHLL, "SSHLL, SSHLL2", "0Q0011110IIIIiii101001nnnnnddddd")
//INST(SCVTF_fix_2, "SCVTF (vector, fixed-point)", "0Q0011110IIIIiii111001nnnnnddddd")
//INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd")
//INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
//INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
//INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
//INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")

19
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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@ -28,6 +28,25 @@ bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
return true;
}
bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();
}
if (immh.Bit<3>() && !Q) {
return ReservedValue();
}
const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
const size_t datasize = Q ? 128 : 64;
const u8 shift_amount = static_cast<u8>(2 * esize) - concatenate(immh, immb).ZeroExtend<u8>();
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.VectorLogicalShiftRight(esize, operand, shift_amount);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();