A32: Implement ASIMD modified immediate functions
Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.
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Lioncash
merry
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commit
fc112e61f2
4 changed files with 155 additions and 11 deletions
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@ -123,6 +123,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
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frontend/A32/location_descriptor.h
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frontend/A32/PSR.h
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frontend/A32/translate/impl/asimd_load_store_structures.cpp
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frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
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frontend/A32/translate/impl/asimd_three_same.cpp
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frontend/A32/translate/impl/asimd_two_regs_misc.cpp
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frontend/A32/translate/impl/barrier.cpp
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@ -108,17 +108,7 @@ INST(asimd_VSWP, "VSWP", "111100111D110010dddd000
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//INST(asimd_VCVT_integer, "VCVT (integer)", "111100111-11--11----011xxx-0----") // ASIMD
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// One register and modified immediate
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//INST(asimd_VMOV_imm, "VMOV (immediate)", "1111001a1-000bcd----0xx00-01efgh") // ASIMD
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//INST(asimd_VORR_imm, "VORR (immediate)", "1111001a1-000bcd----0xx10-01efgh") // ASIMD
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//INST(asimd_VMOV_imm, "VMOV (immediate)", "1111001a1-000bcd----10x00-01efgh") // ASIMD
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//INST(asimd_VORR_imm, "VORR (immediate)", "1111001a1-000bcd----10x10-01efgh") // ASIMD
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//INST(asimd_VMOV_imm, "VMOV (immediate)", "1111001a1-000bcd----11xx0-01efgh") // ASIMD
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//INST(asimd_VMVN_imm, "VMVN (immediate)", "1111001a1-000bcd----0xx00-11efgh") // ASIMD
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//INST(asimd_VBIC_imm, "VBIC (immediate)", "1111001a1-000bcd----0xx10-11efgh") // ASIMD
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//INST(asimd_VMVN_imm, "VMVN (immediate)", "1111001a1-000bcd----10x00-11efgh") // ASIMD
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//INST(asimd_VBIC_imm, "VBIC (immediate)", "1111001a1-000bcd----10x10-11efgh") // ASIMD
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//INST(asimd_VMVN_imm, "VMVN (immediate)", "1111001a1-000bcd----110x0-11efgh") // ASIMD
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//INST(asimd_VMOV_imm, "VMOV (immediate)", "1111001a1-000bcd----11100-11efgh") // ASIMD
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INST(asimd_VMOV_imm, "VBIC, VMOV, VMVN, VORR (immediate)", "1111001a1D000bcdVVVVmmmm0Qo1efgh") // ASIMD
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// Advanced SIMD load/store structures
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INST(v8_VST_multiple, "VST{1-4} (multiple)", "111101000D00nnnnddddxxxxzzaammmm") // v8
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@ -0,0 +1,149 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2020 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/assert.h"
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_arm.h"
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namespace Dynarmic::A32 {
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namespace {
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ExtReg ToExtRegD(size_t base, bool bit) {
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return ExtReg::D0 + (base + (bit ? 16 : 0));
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}
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u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) {
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switch (cmode.Bits<1, 3>()) {
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case 0b000:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 32);
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case 0b001:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 32);
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case 0b010:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 16, 32);
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case 0b011:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 24, 32);
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case 0b100:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 16);
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case 0b101:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 16);
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case 0b110:
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if (!cmode.Bit<0>()) {
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return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 8) | Common::Ones<u64>(8), 32);
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}
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return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 16) | Common::Ones<u64>(16), 32);
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case 0b111:
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if (!cmode.Bit<0>() && !op) {
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 8);
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}
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if (!cmode.Bit<0>() && op) {
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u64 result = 0;
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result |= imm8.Bit<0>() ? Common::Ones<u64>(8) << (0 * 8) : 0;
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result |= imm8.Bit<1>() ? Common::Ones<u64>(8) << (1 * 8) : 0;
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result |= imm8.Bit<2>() ? Common::Ones<u64>(8) << (2 * 8) : 0;
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result |= imm8.Bit<3>() ? Common::Ones<u64>(8) << (3 * 8) : 0;
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result |= imm8.Bit<4>() ? Common::Ones<u64>(8) << (4 * 8) : 0;
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result |= imm8.Bit<5>() ? Common::Ones<u64>(8) << (5 * 8) : 0;
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result |= imm8.Bit<6>() ? Common::Ones<u64>(8) << (6 * 8) : 0;
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result |= imm8.Bit<7>() ? Common::Ones<u64>(8) << (7 * 8) : 0;
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return result;
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}
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if (cmode.Bit<0>() && !op) {
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u64 result = 0;
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result |= imm8.Bit<7>() ? 0x80000000 : 0;
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result |= imm8.Bit<6>() ? 0x3E000000 : 0x40000000;
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result |= imm8.Bits<0, 5, u64>() << 19;
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return Common::Replicate<u64>(result, 32);
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}
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if (cmode.Bit<0>() && op) {
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u64 result = 0;
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result |= imm8.Bit<7>() ? 0x80000000'00000000 : 0;
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result |= imm8.Bit<6>() ? 0x3FC00000'00000000 : 0x40000000'00000000;
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result |= imm8.Bits<0, 5, u64>() << 48;
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return result;
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}
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}
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UNREACHABLE();
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}
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} // Anonymous namespace
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bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd,
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Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h) {
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if (Q && Common::Bit<0>(Vd)) {
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return UndefinedInstruction();
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}
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const auto d_reg = ToExtRegD(Vd, D);
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const size_t regs = Q ? 2 : 1;
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const auto imm = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h));
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// VMOV
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const auto mov = [&] {
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const auto imm64 = ir.Imm64(imm);
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for (size_t i = 0; i < regs; i++) {
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ir.SetExtendedRegister(d_reg + i, imm64);
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}
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return true;
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};
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// VMVN
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const auto mvn = [&] {
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const auto imm64 = ir.Imm64(~imm);
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for (size_t i = 0; i < regs; i++) {
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ir.SetExtendedRegister(d_reg + i, imm64);
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}
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return true;
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};
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// VORR
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const auto orr = [&] {
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const auto imm64 = ir.Imm64(imm);
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for (size_t i = 0; i < regs; i++) {
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const auto d_index = d_reg + i;
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const auto reg_value = ir.GetExtendedRegister(d_index);
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ir.SetExtendedRegister(d_index, ir.Or(reg_value, imm64));
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}
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return true;
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};
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// VBIC
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const auto bic = [&] {
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const auto imm64 = ir.Imm64(~imm);
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for (size_t i = 0; i < regs; i++) {
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const auto d_index = d_reg + i;
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const auto reg_value = ir.GetExtendedRegister(d_index);
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ir.SetExtendedRegister(d_index, ir.And(reg_value, imm64));
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}
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return true;
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};
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switch (concatenate(cmode, Imm<1>{op}).ZeroExtend()) {
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case 0b00000: case 0b00100:
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case 0b01000: case 0b01100:
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case 0b10000: case 0b10100:
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case 0b11000: case 0b11010:
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case 0b11100: case 0b11101:
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case 0b11110:
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return mov();
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case 0b11111:
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return UndefinedInstruction();
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case 0b00001: case 0b00101:
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case 0b01001: case 0b01101:
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case 0b10001: case 0b10101:
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case 0b11001: case 0b11011:
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return mvn();
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case 0b00010: case 0b00110:
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case 0b01010: case 0b01110:
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case 0b10010: case 0b10110:
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return orr();
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case 0b00011: case 0b00111:
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case 0b01011: case 0b01111:
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case 0b10011: case 0b10111:
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return bic();
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}
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UNREACHABLE();
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}
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} // namespace Dynarmic::A32
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@ -429,6 +429,10 @@ struct ArmTranslatorVisitor final {
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bool vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
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bool vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
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// Advanced SIMD one register, modified immediate
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bool asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd,
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Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h);
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// Advanced SIMD three register variants
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bool asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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