mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ir: Add opcodes for performing vector absolute floating-point values

Browse source 
This will be usable for implementing FACGE and FACGT
This commit is contained in:
Lioncash 2018-07-06 21:55:42 -04:00 committed by MerryMage
parent 0bee648b4f
commit fc731dddae
4 changed files with 36 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
src/backend_x64/emit_x64_vector_floating_point.cpp
View file

@ -195,6 +195,28 @@ void EmitX64::EmitFPVectorAbsoluteDifference64(EmitContext& ctx, IR::Inst* inst)
ctx.reg_alloc.DefineValue(inst, a); ctx.reg_alloc.DefineValue(inst, a);
} }
void EmitX64::EmitFPVectorAbs32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Address mask = code.MConst(xword, 0x7FFFFFFF7FFFFFFF, 0x7FFFFFFF7FFFFFFF);
code.andps(a, mask);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitFPVectorAbs64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Address mask = code.MConst(xword, 0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF);
code.andpd(a, mask);
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitFPVectorAdd32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPVectorAdd32(EmitContext& ctx, IR::Inst* inst) {
EmitVectorOperation32(code, ctx, inst, &Xbyak::CodeGenerator::addps); EmitVectorOperation32(code, ctx, inst, &Xbyak::CodeGenerator::addps);
} }

11
src/frontend/ir/ir_emitter.cpp
View file

@ -1491,6 +1491,17 @@ U64 IREmitter::FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_con
return Inst<U64>(Opcode::FPU32ToDouble, a, Imm1(round_to_nearest)); return Inst<U64>(Opcode::FPU32ToDouble, a, Imm1(round_to_nearest));
} }
U128 IREmitter::FPVectorAbs(size_t esize, const U128& a) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorAbs32, a);
case 64:
return Inst<U128>(Opcode::FPVectorAbs64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorAbsoluteDifference(size_t esize, const U128& a, const U128& b) { U128 IREmitter::FPVectorAbsoluteDifference(size_t esize, const U128& a, const U128& b) {
switch (esize) { switch (esize) {
case 32: case 32:

1
src/frontend/ir/ir_emitter.h
View file

@ -273,6 +273,7 @@ public:
U64 FPS32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled); U64 FPS32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U64 FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled); U64 FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U128 FPVectorAbs(size_t esize, const U128& a);
U128 FPVectorAbsoluteDifference(size_t esize, const U128& a, const U128& b); U128 FPVectorAbsoluteDifference(size_t esize, const U128& a, const U128& b);
U128 FPVectorAdd(size_t esize, const U128& a, const U128& b); U128 FPVectorAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorDiv(size_t esize, const U128& a, const U128& b); U128 FPVectorDiv(size_t esize, const U128& a, const U128& b);

2
src/frontend/ir/opcodes.inc
View file

@ -396,6 +396,8 @@ OPCODE(FPU32ToDouble, T::U64, T::U32, T::U
OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 ) OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 )
// Floating-point vector instructions // Floating-point vector instructions
OPCODE(FPVectorAbs32, T::U128, T::U128 )
OPCODE(FPVectorAbs64, T::U128, T::U128 )
OPCODE(FPVectorAbsoluteDifference32, T::U128, T::U128, T::U128 ) OPCODE(FPVectorAbsoluteDifference32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorAbsoluteDifference64, T::U128, T::U128, T::U128 ) OPCODE(FPVectorAbsoluteDifference64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorAdd32, T::U128, T::U128, T::U128 ) OPCODE(FPVectorAdd32, T::U128, T::U128, T::U128 )