EmitPackedHalvingAddU8: Add SSE2 implementation
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1 changed files with 35 additions and 16 deletions
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@ -1737,25 +1737,44 @@ void EmitX64::EmitPackedSubS16(RegAlloc& reg_alloc, IR::Block& block, IR::Inst*
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void EmitX64::EmitPackedHalvingAddU8(RegAlloc& reg_alloc, IR::Block&, IR::Inst* inst) {
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auto args = reg_alloc.GetArgumentInfo(inst);
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Xbyak::Reg32 reg_a = reg_alloc.UseScratchGpr(args[0]).cvt32();
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Xbyak::Reg32 reg_b = reg_alloc.UseGpr(args[1]).cvt32();
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Xbyak::Reg32 xor_a_b = reg_alloc.ScratchGpr().cvt32();
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Xbyak::Reg32 and_a_b = reg_a;
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Xbyak::Reg32 result = reg_a;
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if (args[0].IsInXmm() || args[1].IsInXmm()) {
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Xbyak::Xmm xmm_a = reg_alloc.UseScratchXmm(args[0]);
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Xbyak::Xmm xmm_b = reg_alloc.UseScratchXmm(args[1]);
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Xbyak::Xmm ones = reg_alloc.ScratchXmm();
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// This relies on the equality x+y == ((x&y) << 1) + (x^y).
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// Note that x^y always contains the LSB of the result.
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// Since we want to calculate (x+y)/2, we can instead calculate (x&y) + ((x^y)>>1).
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// We mask by 0x7F to remove the LSB so that it doesn't leak into the field below.
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// Since,
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// pavg(a, b) == (a + b + 1) >> 1
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// Therefore,
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// ~pavg(~a, ~b) == (a + b) >> 1
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code->mov(xor_a_b, reg_a);
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code->and_(and_a_b, reg_b);
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code->xor_(xor_a_b, reg_b);
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code->shr(xor_a_b, 1);
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code->and_(xor_a_b, 0x7F7F7F7F);
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code->add(result, xor_a_b);
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code->pcmpeqb(ones, ones);
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code->pxor(xmm_a, ones);
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code->pxor(xmm_b, ones);
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code->pavgb(xmm_a, xmm_b);
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code->pxor(xmm_a, ones);
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reg_alloc.DefineValue(inst, result);
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reg_alloc.DefineValue(inst, xmm_a);
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} else {
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Xbyak::Reg32 reg_a = reg_alloc.UseScratchGpr(args[0]).cvt32();
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Xbyak::Reg32 reg_b = reg_alloc.UseGpr(args[1]).cvt32();
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Xbyak::Reg32 xor_a_b = reg_alloc.ScratchGpr().cvt32();
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Xbyak::Reg32 and_a_b = reg_a;
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Xbyak::Reg32 result = reg_a;
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// This relies on the equality x+y == ((x&y) << 1) + (x^y).
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// Note that x^y always contains the LSB of the result.
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// Since we want to calculate (x+y)/2, we can instead calculate (x&y) + ((x^y)>>1).
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// We mask by 0x7F to remove the LSB so that it doesn't leak into the field below.
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code->mov(xor_a_b, reg_a);
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code->and_(and_a_b, reg_b);
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code->xor_(xor_a_b, reg_b);
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code->shr(xor_a_b, 1);
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code->and_(xor_a_b, 0x7F7F7F7F);
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code->add(result, xor_a_b);
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reg_alloc.DefineValue(inst, result);
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}
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}
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void EmitX64::EmitPackedHalvingAddU16(RegAlloc& reg_alloc, IR::Block&, IR::Inst* inst) {
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