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A64: Implement UCVTF (vector, integer), scalar variant

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This commit is contained in:
MerryMage 2018-02-20 19:04:56 +00:00
parent be57608353
commit fd8f4c1195
3 changed files with 27 additions and 2 deletions
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1
src/CMakeLists.txt
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@ -101,6 +101,7 @@ add_library(dynarmic
frontend/A64/translate/impl/simd_permute.cpp frontend/A64/translate/impl/simd_permute.cpp
frontend/A64/translate/impl/simd_scalar_pairwise.cpp frontend/A64/translate/impl/simd_scalar_pairwise.cpp
frontend/A64/translate/impl/simd_scalar_three_same.cpp frontend/A64/translate/impl/simd_scalar_three_same.cpp
frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
frontend/A64/translate/impl/simd_shift_by_immediate.cpp frontend/A64/translate/impl/simd_shift_by_immediate.cpp
frontend/A64/translate/impl/simd_three_same.cpp frontend/A64/translate/impl/simd_three_same.cpp
frontend/A64/translate/impl/simd_two_register_misc.cpp frontend/A64/translate/impl/simd_two_register_misc.cpp

4
src/frontend/A64/decoder/a64.inc
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@ -356,7 +356,7 @@ INST(DUP_elt_1, "DUP (element)", "01011
//INST(FACGT_1, "FACGT", "01111110110mmmmm001011nnnnnddddd") //INST(FACGT_1, "FACGT", "01111110110mmmmm001011nnnnnddddd")
//INST(FACGT_2, "FACGT", "011111101z1mmmmm111011nnnnnddddd") //INST(FACGT_2, "FACGT", "011111101z1mmmmm111011nnnnnddddd")
// Data Processing - FP and SIMD - Two register misc // Data Processing - FP and SIMD - Scalar two register misc
//INST(FCVTNS_1, "FCVTNS (vector)", "0101111001111001101010nnnnnddddd") //INST(FCVTNS_1, "FCVTNS (vector)", "0101111001111001101010nnnnnddddd")
//INST(FCVTNS_2, "FCVTNS (vector)", "010111100z100001101010nnnnnddddd") //INST(FCVTNS_2, "FCVTNS (vector)", "010111100z100001101010nnnnnddddd")
//INST(FCVTMS_1, "FCVTMS (vector)", "0101111001111001101110nnnnnddddd") //INST(FCVTMS_1, "FCVTMS (vector)", "0101111001111001101110nnnnnddddd")
@ -386,7 +386,7 @@ INST(DUP_elt_1, "DUP (element)", "01011
//INST(FCVTAU_1, "FCVTAU (vector)", "0111111001111001110010nnnnnddddd") //INST(FCVTAU_1, "FCVTAU (vector)", "0111111001111001110010nnnnnddddd")
//INST(FCVTAU_2, "FCVTAU (vector)", "011111100z100001110010nnnnnddddd") //INST(FCVTAU_2, "FCVTAU (vector)", "011111100z100001110010nnnnnddddd")
//INST(UCVTF_int_1, "UCVTF (vector, integer)", "0111111001111001110110nnnnnddddd") //INST(UCVTF_int_1, "UCVTF (vector, integer)", "0111111001111001110110nnnnnddddd")
//INST(UCVTF_int_2, "UCVTF (vector, integer)", "011111100z100001110110nnnnnddddd") INST(UCVTF_int_2, "UCVTF (vector, integer)", "011111100z100001110110nnnnnddddd")
//INST(FCMGE_zero_1, "FCMGE (zero)", "0111111011111000110010nnnnnddddd") //INST(FCMGE_zero_1, "FCMGE (zero)", "0111111011111000110010nnnnnddddd")
//INST(FCMGE_zero_2, "FCMGE (zero)", "011111101z100000110010nnnnnddddd") //INST(FCMGE_zero_2, "FCMGE (zero)", "011111101z100000110010nnnnnddddd")
//INST(FCMLE_1, "FCMLE (zero)", "0111111011111000110110nnnnnddddd") //INST(FCMLE_1, "FCMLE (zero)", "0111111011111000110110nnnnnddddd")

24
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp Normal file
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@ -0,0 +1,24 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2018 MerryMage
* This software may be used and distributed according to the terms of the GNU
* General Public License version 2 or any later version.
*/
#include "frontend/A64/translate/impl/impl.h"
namespace Dynarmic::A64 {
bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
const auto esize = sz ? 64 : 32;
IR::U32U64 element = V_scalar(esize, Vn);
if (esize == 32) {
element = ir.FPU32ToSingle(element, false, true);
} else {
return InterpretThisInstruction();
}
V_scalar(esize, Vd, element);
return true;
}
} // namespace Dynarmic::A64