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translate_arm/parallel: Detect UNPREDICTABLE instructions

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This commit is contained in:
MerryMage 2016-08-19 00:40:18 +01:00
parent 2119dfc926
commit fe15cbd50e
1 changed files with 12 additions and 0 deletions
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12
src/frontend/translate/translate_arm/parallel.cpp
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@ -61,6 +61,8 @@ bool ArmTranslatorVisitor::arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
// Parallel Add/Subtract (Saturating) instructions // Parallel Add/Subtract (Saturating) instructions
bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedAddS8(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedAddS8(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);
@ -69,6 +71,8 @@ bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
} }
bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedAddS16(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedAddS16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);
@ -85,6 +89,8 @@ bool ArmTranslatorVisitor::arm_QSAX(Cond cond, Reg n, Reg d, Reg m) {
} }
bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedSubS8(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedSubS8(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);
@ -93,6 +99,8 @@ bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
} }
bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedSubS16(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedSubS16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);
@ -125,6 +133,8 @@ bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
} }
bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedSubU8(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedSubU8(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);
@ -133,6 +143,8 @@ bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
} }
bool ArmTranslatorVisitor::arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedSubU16(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedSubU16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);