thumb32: Implement LDRB variants

src/frontend/A32/decoder/thumb32.inc

@@ -153,11 +153,11 @@ INST(thumb32_PLI_lit,        "PLI (lit)",                "11111001U00111111111ii
 INST(thumb32_PLI_reg,        "PLI (reg)",                "111110010001nnnn1111000000iimmmm")
 INST(thumb32_PLI_imm8,       "PLI (imm8)",               "111110010001nnnn11111100iiiiiiii")
 INST(thumb32_PLI_imm12,      "PLI (imm12)",              "111110011001nnnn1111iiiiiiiiiiii")
-//INST(thumb32_LDRB_lit,       "LDRB (lit)",               "11111000-0011111----------------")
+INST(thumb32_LDRB_lit,       "LDRB (lit)",               "11111000U0011111ttttiiiiiiiiiiii")
-//INST(thumb32_LDRB_reg,       "LDRB (reg)",               "111110000001--------000000------")
+INST(thumb32_LDRB_reg,       "LDRB (reg)",               "111110000001nnnntttt000000iimmmm")
-//INST(thumb32_LDRBT,          "LDRBT",                    "111110000001--------1110--------")
+INST(thumb32_LDRBT,          "LDRBT",                    "111110000001nnnntttt1110iiiiiiii")
-//INST(thumb32_LDRB_imm8,      "LDRB (imm8)",              "111110000001--------1-----------")
+INST(thumb32_LDRB_imm8,      "LDRB (imm8)",              "111110000001nnnntttt1PUWiiiiiiii")
-//INST(thumb32_LDRB_imm12,     "LDRB (imm12)",             "111110001001--------------------")
+INST(thumb32_LDRB_imm12,     "LDRB (imm12)",             "111110001001nnnnttttiiiiiiiiiiii")
 //INST(thumb32_LDRSB_lit,      "LDRSB (lit)",              "11111001-0011111----------------")
 //INST(thumb32_LDRSB_reg,      "LDRSB (reg)",              "111110010001--------000000------")
 //INST(thumb32_LDRSBT,         "LDRSBT",                   "111110010001--------1110--------")

src/frontend/A32/translate/impl/thumb32_load_byte.cpp

@@ -78,4 +78,78 @@ bool ThumbTranslatorVisitor::thumb32_PLI_reg([[maybe_unused]] Reg n,
     return PLIHandler(*this);
 }
 
+bool ThumbTranslatorVisitor::thumb32_LDRB_lit(bool U, Reg t, Imm<12> imm12) {
+    const u32 imm32 = imm12.ZeroExtend();
+    const u32 base = ir.AlignPC(4);
+    const u32 address = U ? (base + imm32) : (base - imm32);
+    const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(ir.Imm32(address)));
+
+    ir.SetRegister(t, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
+    if (t == Reg::PC && W) {
+        return UnpredictableInstruction();
+    }
+    if (W && n == t) {
+        return UnpredictableInstruction();
+    }
+    if (!P && !W) {
+        return UndefinedInstruction();
+    }
+
+    const u32 imm32 = imm8.ZeroExtend();
+    const IR::U32 reg_n = ir.GetRegister(n);
+    const IR::U32 offset_address = U ? ir.Add(reg_n, ir.Imm32(imm32))
+                                     : ir.Sub(reg_n, ir.Imm32(imm32));
+    const IR::U32 address = P ? offset_address : reg_n;
+    const IR::U32 data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
+
+    ir.SetRegister(t, data);
+    if (W) {
+        ir.SetRegister(n, offset_address);
+    }
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12) {
+    const auto imm32 = imm12.ZeroExtend();
+    const auto reg_n = ir.GetRegister(n);
+    const auto address = ir.Add(reg_n, ir.Imm32(imm32));
+    const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
+
+    ir.SetRegister(t, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRB_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
+    if (m == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const auto reg_n = ir.GetRegister(n);
+    const auto reg_m = ir.GetRegister(m);
+    const auto offset = ir.LogicalShiftLeft(reg_m, ir.Imm8(imm2.ZeroExtend<u8>()));
+    const auto address = ir.Add(reg_n, offset);
+    const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
+
+    ir.SetRegister(t, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8) {
+    // TODO: Add an unpredictable instruction path if this
+    //       is executed in hypervisor mode if we ever support
+    //       privileged execution modes.
+
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    // Treat it as a normal LDRB, given we don't support
+    // execution levels other than EL0 currently.
+    return thumb32_LDRB_imm8(n, t, true, true, false, imm8);
+}
+
 } // namespace Dynarmic::A32

src/frontend/A32/translate/impl/translate_thumb.h

@@ -214,6 +214,11 @@ struct ThumbTranslatorVisitor final {
     bool thumb32_PLI_imm8(Reg n, Imm<8> imm8);
     bool thumb32_PLI_imm12(Reg n, Imm<12> imm12);
     bool thumb32_PLI_reg(Reg n, Imm<2> imm2, Reg m);
+    bool thumb32_LDRB_lit(bool U, Reg t, Imm<12> imm12);
+    bool thumb32_LDRB_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
+    bool thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
+    bool thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12);
+    bool thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8);
 
     // thumb32 data processing (register) instructions
     bool thumb32_ASR_reg(Reg m, Reg d, Reg s);