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202 commits

Author SHA1 Message Date
Lioncash
f1057aa362 tests: Fix truncation in GetFpcr() 2020-04-22 20:44:38 +01:00
MerryMage
e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage
1749780929 interface: Move Vector typedef to config.h 2020-04-22 20:44:37 +01:00
MerryMage
2a493f8b50 fuzz_with_unicorn: Compare vectors 2020-04-22 20:42:46 +01:00
MerryMage
35aaee6cc6 tests/A64: Randomize vectors 2020-04-22 20:42:46 +01:00
MerryMage
33a02ed91a tests/A64/unicorn: Print interrupt number when InterruptHook is hit 2020-04-22 20:42:46 +01:00
MerryMage
e9f6e7c82c tests/A64: Allow RunTestInstance to start from an arbitrary offset 2020-04-22 20:42:46 +01:00
Thomas Guillemard
896cf44f96 A64: Implement REV, REV32, and REV16 (#126) 2020-04-22 20:42:46 +01:00
MerryMage
7992a319ba A64/tests: Split unicorn sanity checking from other tests 2020-04-22 20:42:45 +01:00
MerryMage
9d42bc3228 tests/A64: Single random instruction: Test branch instructions as well 2020-04-22 20:42:45 +01:00
MerryMage
9f57283a30 A64: Implement SBFM, BFM, UBFM 2020-04-22 20:42:45 +01:00
MerryMage
c34639f33d fuzz_thumb: Off by one error 2020-04-22 20:42:45 +01:00
MerryMage
a59e9ad9c6 travis: Run A64 tests 2020-04-22 20:42:45 +01:00
MerryMage
e99db8e745 tests/A64: Randomize PSTATE.<NZCV> 2020-04-22 20:42:45 +01:00
MerryMage
99b7516c8c testenv: Use format constants 2020-04-22 20:42:45 +01:00
MerryMage
39d083aa87 tests/A64: Unicorn interface fixes 
- Use a std::unique_ptr instead of new/delete.
- UnmappedMemoryHook: Correct range when wraparound of the address space occurs
- UnmappedMemoryHook: Handle case when we attempt to map the same page twice
 2020-04-22 20:42:45 +01:00
MerryMage
d5725de26a tests/A64: Fuzz against unicorn 2020-04-22 20:42:45 +01:00
MerryMage
a0ef6eda19 tests/A64: Move TestEnvironment to own header 2020-04-22 20:42:45 +01:00
MerryMage
2f8d7ae86f tests/a64: Use format constants 2020-04-22 20:42:45 +01:00
MerryMage
72a793f5b0 ir_opt: Split off A32 specific passes 2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5 A64: PSTATE access and tests 2020-04-22 20:42:45 +01:00
MerryMage
0641445e51 A64: Implement logical 2020-04-22 20:42:45 +01:00
MerryMage
d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93 A64: Backend framework 2020-04-22 20:42:44 +01:00
MerryMage
9d15e0a8e1 Final A32 refactor 2020-04-22 20:39:27 +01:00
MerryMage
b3c73e2622 Label A32 specific code appropriately 2020-04-22 20:33:30 +01:00
MerryMage
19a7fb8992 jit_state: Split off CPSR.NZCV 2020-04-22 20:26:40 +01:00
MerryMage
6adc554b53 jit_state: Hide cpsr implementation 2020-04-22 20:26:40 +01:00
MerryMage
256749910f Add AddTicks and GetTicksRemaining callbacks 2020-04-22 20:26:12 +01:00
Mat M
c6d09adcb7 CMakeLists: Derive the source file listings from targets directly (#118) 
This gets rid of the need to store to individual variables before creating
the target itself, cleaning up the variables in the surrounding scope a little bit.
 2020-04-22 20:26:07 +01:00
MerryMage
f734d7000e fuzz_arm: Test SEL alongside packed instructions 2020-04-22 20:26:07 +01:00
MerryMage
814e378249 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2020-04-22 20:26:07 +01:00
MerryMage
93cf180a44 skyeye: Correct assumption that VFP_REG_ZERO will always be zero 2020-04-22 20:26:07 +01:00
MerryMage
993e142c6b disassembler: Fix RegList 2017-08-05 01:57:29 +01:00
MerryMage
c6c980dfd7 fuzz_arm: Add vsub test 2017-04-02 12:38:38 +01:00
Lynn
fd068ed6b8 Ranged cache invalidation 2017-03-20 11:58:25 +00:00
Lioncash
5a02da445a CMakeLists: Only link LLVM libs against the library 
LLVM library code is only used within the main dynarmic library, not the test executable.
 2017-03-11 13:25:14 +00:00
Lioncash
d0efbb9348 CMakeLists: Remove unnecessary linker language specifiers 
This is already inferred by the cmake project being declared a CXX project.
 2017-03-07 18:30:58 +00:00
Lioncash
9906be746f CMakeLists: Make boost an interface library target 
Gets rid of the use of a non-target include and makes libraries
explicitly link against the identifier name in order to get includes.
 2017-03-04 11:52:32 +00:00
Lioncash
f9e7e85308 externals: Make catch an interface target 
Eliminates top-level inclusion of the headers with include_directories()
and instead utilizes it on a by-target basis using target_include_directories().
 2017-02-26 13:43:47 +00:00
MerryMage
2449468ede fuzz_arm: Dump state when exception is thrown 2017-02-25 11:55:27 +00:00
MerryMage
e8b6e76fbf CMakeLists: Drop -Wno-unused-parameter 2017-02-22 23:52:18 +00:00
MerryMage
c7f32f9466 dyncom: Correct SXTAB16 and SXTB16 2017-02-18 20:14:42 +00:00
MerryMage
2447f2f360 callbacks: Factorize memory callbacks into inner structure 2017-01-30 21:42:51 +00:00
Fernando Sahmkow
70f4235ee9 Implement UXTAB16 (#78) 2016-12-29 12:15:18 +00:00
MerryMage
36082087de callbacks: Read code using MemoryReadCode callback 2016-12-21 21:39:14 +00:00
MerryMage
b1df70578f fuzz_arm: Add test cases for saturation instructions 2016-12-21 19:51:25 +00:00
MerryMage
410e84434e fuzz_arm: Add tests for QASX, QSAX, UQASX, UQSAX 2016-12-20 21:52:38 +00:00
FernandoS27
8919265d2c Implement SADD8, SADD16, SSUB8, SSUB16, USUB16 2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245 Implemented USAD8 and USADA8 2016-12-20 21:52:38 +00:00
MerryMage
975987f38e fuzz_arm: Add test for edge-case of UASX instruction 2016-12-20 20:04:38 +00:00
MerryMage
821b26e9d2 fuzz_arm: Add test for edge-case of SHSAX instruction 2016-12-20 19:12:21 +00:00
MerryMage
b1d3e7aae9 emit_x64: Refactor patching code 
* Only have a single std::unordered_map for patching information
* Factor patch emitters into own functions
* Implement EmitX64::Unpatch
 2016-12-20 14:06:55 +00:00
MerryMage
cc58666c06 CMakeLists: Use target_compile_options intead of add_compile_options 2016-12-19 00:48:25 +00:00
MerryMage
96e46ba6b5 Implement QADD, QSUB, QDADD, QDSUB 2016-12-15 22:34:29 +00:00
MerryMage
276873bf70 Wrap #pragma warning with #ifdef _MSC_VER .. #endif 2016-12-15 21:36:02 +00:00
MerryMage
91e851a991 CMakeLists: Enable /W4 on MSVC 2016-12-15 20:52:23 +00:00
MerryMage
5c1aab1666 Implement CLZ 
Includes tests
 2016-12-04 22:56:33 +00:00
MerryMage
370f654590 fuzz_arm: Add tests for parallel add/subtract (modulo) 2016-12-04 20:51:12 +00:00
Sebastian Valle
cda25c12b3 Added tests for the ARM parallel halving instructions. (#49) 2016-11-26 17:24:57 +00:00
Sebastian Valle
32615d0eff Implemented the PKHTB and PKHBT instructions with tests. (#40) 2016-11-23 21:45:18 +00:00
Sebastian Valle
d589c63107 Implemented the ARM SEL instruction, with tests. (#39) 
The test for this instruction is very peculiar. As the instruction's behavior depends on the value of the CPSR, we generate a MSR instruction after each SEL instruction to change the CPSR.
 2016-11-23 18:14:07 +00:00
MerryMage
5c8bf5a15d callbacks: CallSVC returns void 2016-09-05 19:15:45 +01:00
Mat M
6d53bb6d7e arm_types: Split out LocationDescriptor (#20) 
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
 2016-09-05 11:54:09 +01:00
Mat M
8c4df46580 FPSCR: Make value constructor explicit (#13) 
Maintains consistency between the PSR helper.
 2016-09-03 12:48:31 +01:00
Mat M
6ec651498d arm: Add PSR helper type (#3) 2016-09-02 17:34:33 +01:00
bunnei
728b4ca0d4 tests: Fix compile errors. (#4) 2016-09-02 08:51:03 +01:00
MerryMage
4321e829d1 callbacks: Add user_arg argument to InterpreterFallback 2016-09-01 02:00:08 +01:00
Lioncash
e1ed160768 test_arm_disassembler: More tests 
Adds tests for
- Half-word multiply and multiply accumulate instructions
- Multiply and multiply accumulate instructions
- Synchronization primitive instructions
 2016-08-28 22:06:52 +01:00
Lioncash
d164184b1e test_arm_disassembler: Add more data processing instruction tests 2016-08-28 20:28:32 +01:00
MerryMage
59a8e14d1c reg_alloc: Correct OpArg::setBit for Reg 2016-08-26 15:23:38 +01:00
MerryMage
ed3a686d1d Implement public header files 2016-08-26 00:44:50 +01:00
MerryMage
130b5510a6 tests/fuzz_arm: Fix MSVC conversion warnings 2016-08-25 17:46:22 +01:00
MerryMage
3caf31d19c skyeye: Fix MSVC conversion warnings 2016-08-25 17:43:59 +01:00
MerryMage
ec4c91a92b skyeye: Disable MSVC warning C4200 2016-08-25 17:38:17 +01:00
Lioncash
0e12fb6a56 basic_block: Move all variables behind a public interface 2016-08-25 16:14:37 +01:00
MerryMage
7d181f46ce fuzz_arm: Print more than one IR basic block on failure 2016-08-25 13:00:46 +01:00
MerryMage
8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
Lioncash
1bedd3bd7f CMakeLists: Clean up 
Moves functions out of the main CMakeLists file into module files that
can just be included whenever necessary. This also uses the CMake
provided variables for enforcing compiler requirements.
 2016-08-22 15:55:39 +01:00
MerryMage
74246cc3bf tests/fuzz_arm: Randomize rounding mode in initial_fpscr 2016-08-22 15:54:22 +01:00
MerryMage
f014f3b7d4 tests/fuzz_arm: Update FPSCR in InterpreterFallback 2016-08-22 15:54:21 +01:00
MerryMage
7a8dd9532d skyeye: Read-after-write in SMLA 
In the case when RD === RN, RD was updated before AddOverflow was called
to check for an overflow, resulting in an incorrect state of the Q flag.

This is reapplying a patch from f12578b9ab
that was lost during the 20e253ece2 update
 2016-08-22 15:54:17 +01:00
MerryMage
20e253ece2 tests/skyeye_interpreter: Update Skyeye (22-08-1016) 
Matches the version of Skyeye in citra commit
7b4dcacbb2006de6483e982b21956a8f3098aa1d
 2016-08-22 14:07:54 +01:00
Tillmann Karras
dad7724b86 TranlateArm: implement remaining multiplies 
SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD,
SMUAD, SMUSD
 2016-08-19 01:08:38 +01:00
Tillmann Karras
f12578b9ab skyeye: fix read-after-write conflicts 2016-08-19 01:08:29 +01:00
MerryMage
4acc481463 translate_arm/load_store: Handle unpredictable instructions 
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:

a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors

I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
 2016-08-19 00:59:02 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
bunnei
30f3d869cc TranslateArm: Implement VPUSH and VPOP. 2016-08-13 19:37:03 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
b4c586d5ef TranslateArm: VSTR: Correct behaviour in big-endian mode 2016-08-10 16:43:37 +01:00
bunnei
8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
b3bb1d5048 Tests: Tidy up ARM fuzz tests 2016-08-07 21:55:38 +01:00
MerryMage
4dcd1d1859 Arm: BLX is UNPREDICTABLE when Rm is PC 2016-08-07 20:50:33 +01:00
MerryMage
1af5bef32c TranslateArm: Implement BLX (imm), BLX (reg) and BXJ 2016-08-07 20:40:31 +01:00
MerryMage
3a465ba4a8 VFP: Implement VLDR 2016-08-07 19:59:35 +01:00