Subv
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77761ba032
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Added the format strings for LDRT encodings A1 and A2.
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2016-07-18 14:01:18 -05:00 |
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MerryMage
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14dcb18bbe
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Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)
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2016-07-18 18:48:08 +01:00 |
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MerryMage
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a605a43ef9
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Implement Thumb Instructions: STRH (imm), LDRH (imm)
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2016-07-18 18:28:52 +01:00 |
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MerryMage
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f9755870bb
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Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)
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2016-07-18 18:02:02 +01:00 |
|
Merry
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3b8790bf29
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Merged in Subv/dynarmic/small_opt (pull request #3)
Pass the current IR::Block by reference to the emitter.
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2016-07-18 17:38:12 +01:00 |
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MerryMage
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dfef65d98f
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Implement thumb POP instruction
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2016-07-18 17:37:48 +01:00 |
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Subv
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703a46ec99
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Pass the current IR::Block by reference to the emitter.
This avoids calling the copy constructor more times than needed.
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2016-07-18 11:27:33 -05:00 |
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MerryMage
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f7e3d7b8d2
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Implement Thumb PUSH instruction
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2016-07-18 15:11:16 +01:00 |
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MerryMage
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9109b226af
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Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)
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2016-07-18 11:16:12 +01:00 |
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MerryMage
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c18a3eeab4
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Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
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2016-07-18 10:38:22 +01:00 |
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MerryMage
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bf99ddd065
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Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic
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2016-07-18 10:33:52 +01:00 |
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MerryMage
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28a201da16
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Implement Thumb ADR instruction
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2016-07-18 09:25:33 +01:00 |
|
Merry
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6708960aeb
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Merged in Subv/dynarmic/rev (pull request #2)
Implemented ARM REV and REVSH instructions, with tests.
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2016-07-17 22:13:36 +01:00 |
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Subv
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0cdf5fe751
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Implemented ARM REV and REVSH instructions, with tests.
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2016-07-17 14:45:42 -05:00 |
|
Merry
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24aa24b1bc
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Merged in Subv/dynarmic (pull request #1)
Implemented ARM CMP (imm) instruction.
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2016-07-17 19:43:49 +01:00 |
|
Subv
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7f09510945
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Implemented ARM CMP (imm) instruction.
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2016-07-17 13:29:37 -05:00 |
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MerryMage
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3720da4e19
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Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
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2016-07-16 19:23:42 +01:00 |
|
MerryMage
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866dce0f23
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tests/Thumb: Add revsh (thumb) test
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2016-07-16 19:22:57 +01:00 |
|
MerryMage
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22b1bd7cc7
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tests/Skyeye: Fix thumb REVSH translation
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2016-07-16 19:22:09 +01:00 |
|
MerryMage
|
3ef9da9a92
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Docs: Design documentation
|
2016-07-15 16:47:13 +01:00 |
|
MerryMage
|
4b1c27e64f
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Implement arm_ADC_imm
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2016-07-14 20:02:41 +01:00 |
|
MerryMage
|
63242924fc
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Implement thumb16_SVC
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2016-07-14 15:01:30 +01:00 |
|
MerryMage
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181f78f36e
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Common: Remove src/common/logging/log.*
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2016-07-14 14:55:08 +01:00 |
|
MerryMage
|
07eaf100ba
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Reorganise src/frontend: Add subdirectories disassembler and translate
|
2016-07-14 14:39:43 +01:00 |
|
MerryMage
|
9b2aff166a
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Implement arm_SVC
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2016-07-14 14:29:46 +01:00 |
|
MerryMage
|
672ffb93d0
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frontend/translator: Skeleton for Arm translator
|
2016-07-14 13:28:20 +01:00 |
|
MerryMage
|
7d7751c157
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Allow IR blocks to require a cond for block entry.
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
|
2016-07-14 12:52:53 +01:00 |
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MerryMage
|
4ab4ca58f9
|
backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight
|
2016-07-14 09:02:27 +01:00 |
|
MerryMage
|
08e848044d
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backend_x64: Inline Routines::GenReturnFromRunCode into emitted code
|
2016-07-12 16:46:27 +01:00 |
|
MerryMage
|
619b451902
|
clang support
|
2016-07-12 14:31:43 +01:00 |
|
MerryMage
|
8449deb0bc
|
MSVC support
|
2016-07-12 13:28:09 +01:00 |
|
MerryMage
|
44352680c6
|
s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones
|
2016-07-12 11:09:34 +01:00 |
|
MerryMage
|
6e46e7899a
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Translate/Thumb: Fallback to interpreter for Thumb32 instructions
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2016-07-12 11:02:45 +01:00 |
|
MerryMage
|
60455f9bbc
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tests/fuzz_thumb: Fuzz instructions that may change the PC
|
2016-07-12 10:58:57 +01:00 |
|
MerryMage
|
09420d190b
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IR: Implement IR microinstructions ALUWritePC and LoadWritePC
|
2016-07-12 10:58:14 +01:00 |
|
MerryMage
|
65d27f3486
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tests: Add some Arm tests
|
2016-07-12 09:12:56 +01:00 |
|
MerryMage
|
f85b86486b
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frontend/TranslateArm: Just interpret all ARM instructions
|
2016-07-12 09:11:35 +01:00 |
|
MerryMage
|
1410221b47
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Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
|
2016-07-11 23:11:05 +01:00 |
|
MerryMage
|
e7922e4fef
|
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
|
2016-07-11 22:43:53 +01:00 |
|
MerryMage
|
cbcf61a9e6
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backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI
|
2016-07-11 15:28:10 +01:00 |
|
MerryMage
|
d92a771e3c
|
tests/fuzz_thumb: Implement verification of memory writes
|
2016-07-10 13:29:15 +08:00 |
|
MerryMage
|
f0f14fa5e8
|
Implement thumb1_MOV_reg
|
2016-07-10 13:10:06 +08:00 |
|
MerryMage
|
8920ce79b9
|
Implement thumb_CMP_reg_t2
|
2016-07-10 12:23:16 +08:00 |
|
MerryMage
|
3f7290db16
|
tests/fuzz_thumb: Change how test instructions are generated (Introduce InstructionGenerator struct)
|
2016-07-10 12:17:02 +08:00 |
|
MerryMage
|
ac2fb6b925
|
Implement thumb1_MVN_reg
|
2016-07-10 10:49:01 +08:00 |
|
MerryMage
|
d11df9067d
|
Implement thumb1_BIC_reg
|
2016-07-10 10:44:45 +08:00 |
|
MerryMage
|
98a64a92b1
|
Implement thumb1_ORR_reg
|
2016-07-10 09:06:38 +08:00 |
|
MerryMage
|
3fe46d2c6f
|
Implement thumb1_CMN_reg
|
2016-07-10 08:55:56 +08:00 |
|
MerryMage
|
641dbf8eb4
|
Implement thumb1_CMP_reg
|
2016-07-10 08:52:28 +08:00 |
|
MerryMage
|
46408267c3
|
Implement thumb1_RSB_imm
|
2016-07-10 08:44:07 +08:00 |
|