MerryMage
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68f46c8334
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backend_x64: Use a reference to BlockOfCode instead of a pointer
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
8931ee346b
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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75b8a76630
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a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
6414736a8d
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emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ebfc51c609
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IR: Implement VectorSetElement{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab9b5fb8aa
|
Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
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2020-04-22 20:46:12 +01:00 |
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Lioncash
|
af1384d700
|
A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
64761dbc72
|
scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
bafb39ebc5
|
A64: Add Disassemble method
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
f023bbb893
|
A32: Add ExceptionRaised IR instruction and use it
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2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
d7044bc751
|
assert: Use fmt in ASSERT_MSG
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
52268298a8
|
a64_emit_x64: Perform RSB predictions
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
98ec9c5f90
|
A32: Change UserCallbacks to be similar to A64's interface
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
b9ce660113
|
reg_alloc: std::move RegAlloc's function argument
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
ed561d6653
|
General: Add missing override specifiers
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
b2d99eddc6
|
EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
54de64f5bf
|
a64_emit_x64: bug: x64 sign-extends 32-bit immediates
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
6fc228f7fd
|
ir_opt: Add A64 Get/Set Elimination Pass
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
af793c2527
|
{a32,a64}_interface: Predict entrypoint
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7734cf1050
|
A64: Implement EXTR
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
d497464c9f
|
a64_jitstate: Have 128-bit wide spills
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
b513b2ef05
|
IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
16fa2cd8f6
|
a64_emit_x64: Use xword from Xbyak::util
|
2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
d5283e46e8
|
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
4ce9c65cfb
|
reg_alloc: Use std::exchange
|
2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
|
e0c12ec2ad
|
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
d124a1d761
|
emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable
For CPUs that didn't support SSE4.1, this was a bug.
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
01a26fa644
|
fixup: travis: Test with disabled CPU feature detection
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
30936f5e94
|
travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
285fd22c30
|
IR: Add IR instruction VectorZeroUpper
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
da3e9a5704
|
a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
|
2020-04-22 20:44:37 +01:00 |
|
FernandoS27
|
ab84524806
|
Implemented SDIV and UDIV instructions
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
f698848e26
|
IR: Add IR instructions A64Memory{Read,Write}128
Add the Windows ABI implementation
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
e1df7ae621
|
IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
e00a522cba
|
IR: Add IR instruction VectorGetElement{8,16,32,64}
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
28ccd85e5c
|
IR: Add IR instruction ZeroExtendToQuad
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
af848c627d
|
block_of_code: Add ABI_RETURN2
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
1749780929
|
interface: Move Vector typedef to config.h
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
793753bf63
|
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
|
2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
8ee854232c
|
General: Default constructors and destructors where applicable
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
db30e02ac8
|
emit_x64: Extract BlockRangeInformation, remove template parameter
|
2020-04-22 20:44:36 +01:00 |
|
MerryMage
|
58c4a25527
|
emit_x64: Use JitStateInfo
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
eaf545877a
|
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
a554e4a329
|
backend_x64: Split emit_x64
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
b612782445
|
opcodes: Add 64-bit CountLeadingZeroes opcode
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
b08be71775
|
a32/a64_emit_x64: Remove unused includes
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
f81d0a2536
|
A64: Implement AND (vector)
|
2020-04-22 20:42:46 +01:00 |
|