Commit graph

10 commits

Author SHA1 Message Date
Lioncash
7305d13221 A32: Implement ARM-mode RBIT 2020-04-22 21:02:46 +01:00
Lioncash
b2f7a0e7ba A32: Implement ARM-mode SDIV/UDIV
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
2020-04-22 21:02:46 +01:00
V.Kalyuzhny
764a93bf5a Switch boost::optional to std::optional 2020-04-22 20:57:37 +01:00
Lioncash
e30f9816ec A32/decoder: Add missing <algorithm> includes
These includes should be present, as we use std::find_if() within these headers.
2020-04-22 20:53:46 +01:00
MerryMage
71e137715d status_register_access: Add support for bits 0 and 1 of mask to MSR 2020-04-22 20:46:23 +01:00
MerryMage
ff3805e332 A32/decoders: Split instruction list into include file 2020-04-22 20:46:23 +01:00
MerryMage
01c1e9017e T32: Add initial decoder list 2020-04-22 20:46:14 +01:00
MerryMage
ba4a779c62 A32/decoder/arm: bug: Correct bitstring for SRS 2020-04-22 20:46:13 +01:00
Lioncash
67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
MerryMage
b3c73e2622 Label A32 specific code appropriately 2020-04-22 20:33:30 +01:00