MerryMage
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caaf36dfd6
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IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}
This implementation just falls-back to the software floating point implementation.
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2020-04-22 20:46:19 +01:00 |
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Lioncash
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9954d28868
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a64_jitstate: Zero SP and PC on construction of A64JitState
Given we zero out/reset everything else in the struct, do the same for these members to keep initialization consistent
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2020-04-22 20:46:17 +01:00 |
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MerryMage
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e3da92024e
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A64: Implement system registers FPCR and FPSR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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44c3c2312a
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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75b8a76630
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a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d497464c9f
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a64_jitstate: Have 128-bit wide spills
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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67443efb62
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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cb481a3a48
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A64: Implement compare and branch
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2020-04-22 20:42:45 +01:00 |
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MerryMage
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e8bcf72ee5
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A64: PSTATE access and tests
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2020-04-22 20:42:45 +01:00 |
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MerryMage
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d1eb757f93
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A64: Backend framework
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2020-04-22 20:42:44 +01:00 |
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