Lioncash
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d040920727
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Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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40614202e7
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ccef85dbb7
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A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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68f46c8334
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backend_x64: Use a reference to BlockOfCode instead of a pointer
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8931ee346b
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0bb4474fb9
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A64: Implement INS (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d13704fdef
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A64: Implement INS (element)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0642d49919
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A64: Implement SMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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5297027ebe
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A64: Implement UMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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47661b746b
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1fb0957aa3
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A64: Implement FCVT
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ca38225e08
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fuzz_with_unicorn: Skip instructions that need to be interpreted
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4be55b8b84
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A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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a07c05ea51
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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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93fcbdf1e2
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A64: Implement FCMP, FCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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75b8a76630
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a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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429dc24587
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IR: Merge U32 and U64 variants of FP instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ed2bedec43
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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6414736a8d
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emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ebfc51c609
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IR: Implement VectorSetElement{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a5c4fbc783
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A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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744495e23d
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iterator_util: Make Reverse constexpr
C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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ab9b5fb8aa
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Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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af1384d700
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A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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64761dbc72
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scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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bafb39ebc5
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A64: Add Disassemble method
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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cc0eb18a0b
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A32: data_processing: Remove !S assertions
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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865a30eb0d
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A32: Implement BKPT
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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f023bbb893
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A32: Add ExceptionRaised IR instruction and use it
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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7ffbebf290
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A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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d7044bc751
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assert: Use fmt in ASSERT_MSG
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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52268298a8
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a64_emit_x64: Perform RSB predictions
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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98ec9c5f90
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A32: Change UserCallbacks to be similar to A64's interface
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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b9ce660113
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reg_alloc: std::move RegAlloc's function argument
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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ed561d6653
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General: Add missing override specifiers
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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b2d99eddc6
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EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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f4f774f9f6
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a64_get_set_elimination_pass: Simplify algorithm
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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54de64f5bf
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a64_emit_x64: bug: x64 sign-extends 32-bit immediates
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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6fc228f7fd
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ir_opt: Add A64 Get/Set Elimination Pass
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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e01b500aea
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ir_emitter: Allow the insertion point for new instructions to be set
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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af793c2527
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{a32,a64}_interface: Predict entrypoint
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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7734cf1050
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A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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88ae7fce52
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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d497464c9f
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a64_jitstate: Have 128-bit wide spills
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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b513b2ef05
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IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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16fa2cd8f6
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a64_emit_x64: Use xword from Xbyak::util
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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67443efb62
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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7abd673a49
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A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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ba3d6da0c8
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load_store_register_unprivileged: bug: LDTRSW
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2020-04-22 20:44:38 +01:00 |
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