Commit graph

3134 commits

Author SHA1 Message Date
MerryMage
fda4e11887 A32: Implement ASIMD VMOV (general-purpose register to scalar) 2020-06-20 23:40:48 +01:00
MerryMage
7ec22b4e1d A32: Implement ASIMD VMOV (scalar to general-purpose register) 2020-06-20 23:30:56 +01:00
MerryMage
8bbc9fdbb6 A32: Implement ASIMD VTBX 2020-06-20 22:35:31 +01:00
Lioncash
06f7229c57 A32: Implement ASIMD VPADAL (integer) 2020-06-20 22:28:47 +01:00
Lioncash
266c6a2000 A32: Implement ASIMD VPADDL (integer) 2020-06-20 22:28:47 +01:00
Lioncash
4bb286ac23 A32: Implement ASIMD VPADD (integer) 2020-06-20 21:22:14 +01:00
Lioncash
1ffeeeb6a2 A32: Implement ASIMD VMAX/VMIN (integer) 2020-06-20 21:20:47 +01:00
Lioncash
945b757b6c A32: Implement ASIMD VMLA/VMLS (integer) 2020-06-20 21:20:21 +01:00
MerryMage
715db8381f A32: Implement ASIMD VMUL (scalar) 2020-06-20 20:34:08 +01:00
MerryMage
b0beecdd41 A32: Implement ASIMD VTBL 2020-06-20 19:25:14 +01:00
MerryMage
28f27bc19d A32: Implement ASIMD VEXT 2020-06-20 19:05:14 +01:00
MerryMage
e8c460c167 A32: Implement ASIMD VDUP (ARM core register) 2020-06-20 16:02:43 +01:00
MerryMage
15ee562dd0 decoder/asimd: Add misc data-processing instructions 2020-06-20 15:39:00 +01:00
MerryMage
214c1d6002 fuzz_arm: Test testable parts of ASIMD VRECPE and VRSQRTE 2020-06-20 15:17:39 +01:00
MerryMage
92cb4a5a34 A32: Implement ASIMD VRSQRTE 2020-06-20 15:13:22 +01:00
MerryMage
8912496206 fuzz_arm: Unicorn has incorrect VRSQRTS implementation 2020-06-20 15:07:50 +01:00
MerryMage
6f59c2cd8e A32: Implement ASIMD VRECPE 2020-06-20 15:07:06 +01:00
MerryMage
d3dc50d718 A32: Implement ASIMD VRSQRTS 2020-06-20 15:06:06 +01:00
MerryMage
8f506c80c3 A32: Implement ASIMD VRECPS 2020-06-20 14:39:05 +01:00
MerryMage
9eef4f7471 A32: Implement ASIMD VMLA, VMLS (floating-point) 2020-06-20 14:31:06 +01:00
MerryMage
60f6e729ac A32: Implement ASIMD VABD (floating-point) 2020-06-20 14:25:04 +01:00
MerryMage
f58e247ef3 A32: Implement ASIMD VPADD (floating-point) 2020-06-20 14:25:04 +01:00
MerryMage
e006f0a205 A32: Implement ASIMD VSUB (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage
4c939b9d0a A32: Implement ASIMD VADD (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage
5ec8e48593 A32: Implement ASIMD VMUL (floating-point)
* Also add fpcr_controlled arguments to FPVectorMul IR instruction
* Merge ASIMD floating-point instruction implementations
2020-06-20 14:20:28 +01:00
MerryMage
bb4f3aa407 A32: Implement ASIMD VMAX, VMIN (floating-point) 2020-06-20 03:21:07 +01:00
Lioncash
8d067d5d60 A32: Implement ASIMD VMUL (integer and polynomial) 2020-06-20 00:53:56 +01:00
Lioncash
ed6ca58058 A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.

In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-20 00:50:40 +01:00
MerryMage
656419286c ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual} 2020-06-20 00:50:40 +01:00
MerryMage
1b3a70a83c backend/x64: Implement separate MSXCSR for ASIMDStandardValue 2020-06-20 00:00:36 +01:00
MerryMage
d3664b03fe ir_emitter: Default fpcr_controlled arguments to true 2020-06-19 22:51:23 +01:00
Lioncash
794440cf8d A32: Implement ASIMD VRSHL 2020-06-19 21:27:48 +01:00
Lioncash
682621ef1a A32: Implement ASIMD VQSHL (register) 2020-06-19 21:27:48 +01:00
Lioncash
e46fb98cc5 A32: Implement ASIMD VSHL (register) 2020-06-19 21:27:48 +01:00
MerryMage
ad96b2b18d VFPv5: Implement VCVT{A,N,P,M} 2020-06-19 20:31:43 +01:00
MerryMage
6a965b80d6 VFPv5: Implement VRINT{A,N,P,M} 2020-06-19 20:24:13 +01:00
MerryMage
3e252cdbfc VFPv5: Implement VSEL 2020-06-19 19:44:45 +01:00
MerryMage
669d05caca VFPv5: Implement VMINNM 2020-06-19 19:44:45 +01:00
MerryMage
6e7ea151a3 VFPv5: Implement VMAXNM 2020-06-19 19:39:01 +01:00
MerryMage
4df3b2f97f vfp: Add decoders for VFPv5
These instructions were introduced in the Cortex-M7
2020-06-19 19:24:32 +01:00
MerryMage
55c021fe82 emit_x64_aes: AESNI implementations of all opcodes 2020-06-19 12:11:45 +01:00
Lioncash
551e207661 A32: Implement ASIMD VSUB (integer) 2020-06-19 11:31:38 +01:00
Lioncash
4d6f68525d A32: Implement ASIMD VADD (integer) 2020-06-19 11:31:38 +01:00
Lioncash
fbdae61c13 A32: Implement ASIMD VMVN (register)
Fairly straightforward
2020-06-19 11:31:14 +01:00
MerryMage
b759773b3b a32_emit_x64: EmitVAddrLookup: Use 64-bit registers where required 2020-06-19 00:44:52 +01:00
merry
687c604197
Merge pull request #532 from lioncash/shift
A32: Implement several ASIMD shift instructions
2020-06-19 00:22:18 +01:00
MerryMage
7dd9901de2 a32_emit_x64: Incorrect type in ExclusiveWriteMemory 2020-06-19 00:19:46 +01:00
Lioncash
00b2f9b319 asimd: Prevent misdecodes from occurring
Pointed out by Mary when reviewing the shift code.
2020-06-18 15:04:48 -04:00
MerryMage
87f6e412d0 emit_x64_vector: SSE4.1 implementation of EmitVectorPolynomialMultiply{Long}8 2020-06-18 18:44:00 +01:00
MerryMage
f5b41aabc6 emit_x64_vector: Implement EmitVectorPolynomialMultiplyLong64 in terms of pclmulqdq 2020-06-18 18:04:23 +01:00