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148 commits

Author SHA1 Message Date
Lioncash
f42b3ad4a0 A32: Implement ASIMD VBIF (register) 2020-05-16 20:22:12 +01:00
Lioncash
ee9a81dcba A32: Implement ASIMD VBIT (register) 2020-05-16 20:22:12 +01:00
Lioncash
d624059ead A32: Implement ASIMD VBSL (register) 2020-05-16 20:22:12 +01:00
Lioncash
66663cf8e7 asimd_three_same: Collapse all bitwise implementations into a single code path 
Less code and results in only writing the parts that matter once.
 2020-05-16 20:22:12 +01:00
Lioncash
4b5e3437cf A32: Implement ASIMD VEOR (register) 2020-05-16 20:22:12 +01:00
Lioncash
67b284f6fa A32: Implement ASIMD VORN (register) 2020-05-16 20:22:12 +01:00
Lioncash
1fdd90ca2a A32: Implement ASIMD VORR (register) 2020-05-16 20:22:12 +01:00
Lioncash
64fa804dd4 A32: Implement ASIMD VBIC (register) 2020-05-16 20:22:12 +01:00
Lioncash
0441ab81a1 A32: Implement ASIMD VAND (register) 2020-05-16 20:22:12 +01:00
Lioncash
1b25e867ae asimd_load_store_structures: Simplify ToExtRegD() 
ExtReg has a supplied operator+, so we can make use of that instead.
 2020-05-16 11:27:22 -04:00
MerryMage
1a0bc5ba91 A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple) 2020-05-16 14:11:23 +01:00
MerryMage
e7f1a0d408 A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H} 2020-05-15 21:07:36 +01:00
MerryMage
59db2c191a VFPv3: Implement VMOV (immediate) 2020-05-10 15:09:37 +01:00
MerryMage
3c86d58064 VFPv4: Implement VCVTB, VCVTT 2020-05-10 14:45:18 +01:00
MerryMage
010fab9a0e VFPv4: Implement VFMA, VFMS 2020-05-10 14:20:11 +01:00
MerryMage
8e97b10acb VFPv4: Implement VFNMS, VFNMA 2020-05-10 14:14:03 +01:00
MerryMage
6df660c889 fuzz_arm: Ensure all instructions are fuzzed 
* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
 2020-05-10 13:57:39 +01:00
MerryMage
9a38c7324f A32: Add decoders for remaining v7 instructions 2020-05-10 10:50:34 +01:00
MerryMage
dca983803a translate_arm: ConditionPassed: Some instructions emit no microinstructions 2020-04-24 13:12:13 +01:00
MerryMage
94d0d33e02 Fix single stepping for certain instructions 
Several issues:
1. Several terminal instructions did not stop at the end of a single-step block
2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag

We also introduce the enable_optimizations parameter to the A32 frontend.
 2020-04-24 11:44:38 +01:00
MerryMage
5c0bb5cc63 Remove unreachable code (MSVC warnings) 2020-04-23 16:36:34 +01:00
MerryMage
a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage
668a43f815 A32: Detect unpredictable LDM/STM instructions 2020-04-22 21:06:18 +01:00
MerryMage
b6536115ef A32: Add Step 2020-04-22 21:06:17 +01:00
MerryMage
1aa7b62e92 A32/Thumb: Correct behaviour for UDF and Unpredictable instructions 
Raise an exception instead of calling the interpreter and ASSERT-ing respectively.
 2020-04-22 21:04:23 +01:00
MerryMage
396116ee61 A32: Add hook_hint_instructions option 2020-04-22 21:04:23 +01:00
MerryMage
2f2a859615 a32_jitstate: Consolidate upper bits of location descriptor into upper_location_descriptor 
Also solves a performance regression initially introduced by b6e8297e369f2dc4758bafe944e51efb8d1a2552,
primarily due to excessively mismatched load/store sizes causing less than optimal load-to-store forwarding.
 2020-04-22 21:04:23 +01:00
Merry
f252a62c1b Merge pull request #502 from lioncash/header 
General: Remove unnecessary includes
 2020-04-22 21:04:22 +01:00
Lioncash
349d4b577a General: Remove unnecessary includes 
Removes unnecessary header dependencies that have accumulated over time
as changes have been made. Lessens the amount of files that need to be
rebuilt when the headers change.
 2020-04-22 21:04:22 +01:00
Lioncash
dddba94c17 disassembler_arm: Apply const where applicable 2020-04-22 21:04:22 +01:00
Lioncash
9365487797 frontend/A32/ir_emitter: Remove unnecessary includes 
std::initializer_list isn't used anywhere in here, and we can just
forward declare the CoprocReg enum to avoid needing to include the
header.
 2020-04-22 21:04:22 +01:00
Lioncash
bfa8035414 A32/A64: Make public header inclusions consistent 
For all public header inclusions, we use the <> form of including them
as opposed to "", which we typically use for internal headers.
 2020-04-22 21:04:22 +01:00
Lioncash
fb7d33830c A32: Make includes consistent 
Normalizes includes to be relative to the project root, like the rest of
the includes in the project.
 2020-04-22 21:04:22 +01:00
Lioncash
b57ed8917a frontend/A32/types: Remove redundant std::string initializer 
std::string initializes to empty by default. While we're at it, brace a
lone unbraced if statement.
 2020-04-22 21:04:22 +01:00
Lioncash
182ceb2807 General: Make parameter names from declarations and implementations consistent 
Most of the time when this occurs, it's a bug. Thankfully this isn't the
case. However, we can resolve these cases to make the codebase more
consistent.
 2020-04-22 21:04:22 +01:00
Lioncash
b301fcd520 A32/translate/translate: Add missing doxygen parameter string 2020-04-22 21:04:22 +01:00
MerryMage
7d20f3b861 A32/translate_thumb: Split off implementation into thumb16 and thumb32 2020-04-22 21:04:22 +01:00
Lioncash
6b9bf7868a General: Correct typos is code comments 2020-04-22 21:04:22 +01:00
MerryMage
e639aa1583 A32/translate: Rename translate_arm directory to impl 
Mirror what the A64 frontend does.
 2020-04-22 21:04:22 +01:00
MerryMage
5f8eb7c51c A32/location_descriptor: Add CPSR.IT to A32::LocationDescriptor 2020-04-22 21:04:22 +01:00
MerryMage
13f65f55eb PSR: Use Common::ModifyBit{,s} 2020-04-22 21:04:22 +01:00
MerryMage
74633301c1 A32: Add ITState 2020-04-22 21:04:22 +01:00
MerryMage
6e2cd35e4f a32_jitstate: Optimize runtime location descriptor calculation 
Calculation is now one unaligned 64-bit load.
 2020-04-22 21:04:22 +01:00
MerryMage
f178562ee7 a32_jitstate: Remove exception trap enables from FPSCR_MODE_MASK 
We don't currently use this for anything (we do not currently trap
floating point exceptions).

This frees these bits up for other purposes.
 2020-04-22 21:04:21 +01:00
Merry
fd6222f0a1 Merge pull request #500 from lioncash/cbz 
A32: Implement Thumb-1's CBZ/CBNZ instructions
 2020-04-22 21:04:21 +01:00
Merry
bab4e29075 Merge pull request #498 from lioncash/ahp 
A32/location_descriptor: Add AHP bit to the FPSCR mask
 2020-04-22 21:04:21 +01:00
Lioncash
87083af733 general: Remove trailing spaces 
General code-related cleanup. Gets rid of trailing spaces in the
codebase.
 2020-04-22 21:04:21 +01:00
Lioncash
03e6899fd7 A32: Implement Thumb-1's CBZ/CBNZ instructions 
Introduced in ARMv6T2, this allows for short forward branches.
 2020-04-22 21:02:47 +01:00
Lioncash
d02a4e6fc9 A32/location_descriptor: Add AHP bit to the FPSCR mask 
Ensures the alternate half-precision state is preserved within the
location descriptors, which will be necessary when implementing the
half-precision extensions for VFP and NEON.
 2020-04-22 21:02:47 +01:00
Lioncash
bd755ae494 frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit 
This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
 2020-04-22 21:02:47 +01:00