MerryMage
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3720da4e19
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Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
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2016-07-16 19:23:42 +01:00 |
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MerryMage
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9b2aff166a
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Implement arm_SVC
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2016-07-14 14:29:46 +01:00 |
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MerryMage
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7d7751c157
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Allow IR blocks to require a cond for block entry.
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
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2016-07-14 12:52:53 +01:00 |
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MerryMage
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09420d190b
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IR: Implement IR microinstructions ALUWritePC and LoadWritePC
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2016-07-12 10:58:14 +01:00 |
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MerryMage
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1410221b47
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Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
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2016-07-11 23:11:05 +01:00 |
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MerryMage
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e7922e4fef
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Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
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2016-07-11 22:43:53 +01:00 |
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MerryMage
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d11df9067d
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Implement thumb1_BIC_reg
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2016-07-10 10:44:45 +08:00 |
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MerryMage
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98a64a92b1
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Implement thumb1_ORR_reg
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2016-07-10 09:06:38 +08:00 |
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MerryMage
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8145b33882
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Implemented thumb1_ROR_reg
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2016-07-10 08:18:17 +08:00 |
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MerryMage
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92142d5a22
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Implement thumb1_SUB_reg
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2016-07-08 18:49:30 +08:00 |
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MerryMage
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df0c324923
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Implement thumb1_EOR_reg
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2016-07-08 18:14:54 +08:00 |
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MerryMage
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8a0511d297
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Implement thumb1_AND_reg
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2016-07-08 17:44:53 +08:00 |
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MerryMage
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d0b48bfb59
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Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
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2016-07-08 17:44:51 +08:00 |
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MerryMage
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f31b530703
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Fuzz thumb instructions
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2016-07-07 19:01:47 +08:00 |
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MerryMage
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5711e62419
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Implement terminal instructions
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2016-07-07 17:53:09 +08:00 |
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MerryMage
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14388ea690
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Proper implementation of Arm::Translate
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2016-07-04 21:37:50 +08:00 |
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MerryMage
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d743adf518
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Reorganisation, Import Skyeye, This is a mess
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2016-07-04 17:22:11 +08:00 |
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MerryMage
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65df15633d
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First Commit
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2016-07-01 21:01:06 +08:00 |
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