536 lines
21 KiB
C++
536 lines
21 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include <algorithm>
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#include <array>
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#include <cstdio>
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#include <functional>
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#include <tuple>
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#include <vector>
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#include <catch.hpp>
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#include <dynarmic/A32/a32.h>
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#include "common/common_types.h"
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#include "common/fp/fpcr.h"
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#include "common/fp/fpsr.h"
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#include "common/llvm_disassemble.h"
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#include "common/scope_exit.h"
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#include "frontend/A32/ITState.h"
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#include "frontend/A32/location_descriptor.h"
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#include "frontend/A32/translate/translate.h"
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#include "frontend/A32/types.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/location_descriptor.h"
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#include "frontend/ir/opcodes.h"
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#include "fuzz_util.h"
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#include "rand_int.h"
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#include "testenv.h"
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#include "unicorn_emu/a32_unicorn.h"
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// Must be declared last for all necessary operator<< to be declared prior to this.
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#include <fmt/format.h>
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#include <fmt/ostream.h>
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namespace {
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using namespace Dynarmic;
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bool ShouldTestInst(u32 instruction, u32 pc, bool is_thumb, bool is_last_inst, A32::ITState it_state = {}) {
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const A32::LocationDescriptor location = A32::LocationDescriptor{pc, {}, {}}.SetTFlag(is_thumb).SetIT(it_state);
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IR::Block block{location};
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const bool should_continue = A32::TranslateSingleInstruction(block, location, instruction);
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if (!should_continue && !is_last_inst) {
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return false;
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}
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if (auto terminal = block.GetTerminal(); boost::get<IR::Term::Interpret>(&terminal)) {
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return false;
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}
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for (const auto& ir_inst : block) {
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switch (ir_inst.GetOpcode()) {
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case IR::Opcode::A32ExceptionRaised:
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case IR::Opcode::A32CallSupervisor:
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case IR::Opcode::A32CoprocInternalOperation:
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case IR::Opcode::A32CoprocSendOneWord:
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case IR::Opcode::A32CoprocSendTwoWords:
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case IR::Opcode::A32CoprocGetOneWord:
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case IR::Opcode::A32CoprocGetTwoWords:
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case IR::Opcode::A32CoprocLoadWords:
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case IR::Opcode::A32CoprocStoreWords:
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return false;
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// Currently unimplemented in Unicorn
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case IR::Opcode::FPVectorRecipEstimate16:
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case IR::Opcode::FPVectorRSqrtEstimate16:
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case IR::Opcode::VectorPolynomialMultiplyLong64:
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return false;
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default:
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continue;
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}
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}
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return true;
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}
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u32 GenRandomArmInst(u32 pc, bool is_last_inst) {
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static const struct InstructionGeneratorInfo {
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std::vector<InstructionGenerator> generators;
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std::vector<InstructionGenerator> invalid;
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} instructions = []{
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const std::vector<std::tuple<std::string, const char*>> list {
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#define INST(fn, name, bitstring) {#fn, bitstring},
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#include "frontend/A32/decoder/arm.inc"
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#include "frontend/A32/decoder/asimd.inc"
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#include "frontend/A32/decoder/vfp.inc"
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#undef INST
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};
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std::vector<InstructionGenerator> generators;
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std::vector<InstructionGenerator> invalid;
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// List of instructions not to test
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static constexpr std::array do_not_test {
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// Translating load/stores
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"arm_LDRBT", "arm_LDRBT", "arm_LDRHT", "arm_LDRHT", "arm_LDRSBT", "arm_LDRSBT", "arm_LDRSHT", "arm_LDRSHT", "arm_LDRT", "arm_LDRT",
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"arm_STRBT", "arm_STRBT", "arm_STRHT", "arm_STRHT", "arm_STRT", "arm_STRT",
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// Exclusive load/stores
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"arm_LDREXB", "arm_LDREXD", "arm_LDREXH", "arm_LDREX", "arm_LDAEXB", "arm_LDAEXD", "arm_LDAEXH", "arm_LDAEX",
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"arm_STREXB", "arm_STREXD", "arm_STREXH", "arm_STREX", "arm_STLEXB", "arm_STLEXD", "arm_STLEXH", "arm_STLEX",
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"arm_SWP", "arm_SWPB",
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// Elevated load/store multiple instructions.
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"arm_LDM_eret", "arm_LDM_usr",
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"arm_STM_usr",
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// Hint instructions
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"arm_NOP", "arm_PLD_imm", "arm_PLD_reg", "arm_SEV",
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"arm_WFE", "arm_WFI", "arm_YIELD",
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// E, T, J
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"arm_BLX_reg", "arm_BLX_imm", "arm_BXJ", "arm_SETEND",
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// Coprocessor
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"arm_CDP", "arm_LDC", "arm_MCR", "arm_MCRR", "arm_MRC", "arm_MRRC", "arm_STC",
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// System
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"arm_CPS", "arm_RFE", "arm_SRS",
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// Undefined
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"arm_UDF",
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// FPSCR is inaccurate
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"vfp_VMRS",
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// Incorrect Unicorn implementations
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"asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
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"asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
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"vfp_VCVT_from_fixed", // Unicorn does not do round-to-nearest-even for this instruction correctly.
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};
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for (const auto& [fn, bitstring] : list) {
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if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
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invalid.emplace_back(InstructionGenerator{bitstring});
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continue;
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}
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generators.emplace_back(InstructionGenerator{bitstring});
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}
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return InstructionGeneratorInfo{generators, invalid};
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}();
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while (true) {
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const size_t index = RandInt<size_t>(0, instructions.generators.size() - 1);
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const u32 inst = instructions.generators[index].Generate();
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if ((instructions.generators[index].Mask() & 0xF0000000) == 0 && (inst & 0xF0000000) == 0xF0000000) {
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continue;
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}
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if (ShouldTestInst(inst, pc, false, is_last_inst)) {
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return inst;
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}
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}
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}
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std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_state = {}) {
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static const struct InstructionGeneratorInfo {
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std::vector<InstructionGenerator> generators;
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std::vector<InstructionGenerator> invalid;
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} instructions = []{
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const std::vector<std::tuple<std::string, const char*>> list {
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#define INST(fn, name, bitstring) {#fn, bitstring},
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#include "frontend/A32/decoder/thumb16.inc"
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#include "frontend/A32/decoder/thumb32.inc"
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#undef INST
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};
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std::vector<InstructionGenerator> generators;
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std::vector<InstructionGenerator> invalid;
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// List of instructions not to test
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static constexpr std::array do_not_test {
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"thumb16_BKPT",
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"thumb16_IT",
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"thumb16_SETEND",
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};
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for (const auto& [fn, bitstring] : list) {
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if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
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invalid.emplace_back(InstructionGenerator{bitstring});
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continue;
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}
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generators.emplace_back(InstructionGenerator{bitstring});
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}
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return InstructionGeneratorInfo{generators, invalid};
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}();
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while (true) {
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const size_t index = RandInt<size_t>(0, instructions.generators.size() - 1);
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const u32 inst = instructions.generators[index].Generate();
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const bool is_four_bytes = (inst >> 16) != 0;
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if (ShouldTestInst(is_four_bytes ? Common::SwapHalves32(inst) : inst, pc, true, is_last_inst, it_state)) {
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if (is_four_bytes)
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return { static_cast<u16>(inst >> 16), static_cast<u16>(inst) };
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return { static_cast<u16>(inst) };
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}
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}
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}
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template <typename TestEnv>
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Dynarmic::A32::UserConfig GetUserConfig(TestEnv& testenv) {
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Dynarmic::A32::UserConfig user_config;
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user_config.optimizations &= ~OptimizationFlag::FastDispatch;
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user_config.callbacks = &testenv;
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user_config.always_little_endian = true;
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return user_config;
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}
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template <typename TestEnv>
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static void RunTestInstance(Dynarmic::A32::Jit& jit,
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A32Unicorn<TestEnv>& uni,
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TestEnv& jit_env,
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TestEnv& uni_env,
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const typename A32Unicorn<TestEnv>::RegisterArray& regs,
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const typename A32Unicorn<TestEnv>::ExtRegArray& vecs,
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const std::vector<typename TestEnv::InstructionType>& instructions,
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const u32 cpsr,
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const u32 fpscr,
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const size_t ticks_left) {
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const u32 initial_pc = regs[15];
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const u32 num_words = initial_pc / sizeof(typename TestEnv::InstructionType);
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const u32 code_mem_size = num_words + static_cast<u32>(instructions.size());
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jit_env.code_mem.resize(code_mem_size);
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uni_env.code_mem.resize(code_mem_size);
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std::fill(jit_env.code_mem.begin(), jit_env.code_mem.end(), TestEnv::infinite_loop);
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std::fill(uni_env.code_mem.begin(), uni_env.code_mem.end(), TestEnv::infinite_loop);
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std::copy(instructions.begin(), instructions.end(), jit_env.code_mem.begin() + num_words);
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std::copy(instructions.begin(), instructions.end(), uni_env.code_mem.begin() + num_words);
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jit_env.PadCodeMem();
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uni_env.PadCodeMem();
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jit_env.modified_memory.clear();
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uni_env.modified_memory.clear();
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jit_env.interrupts.clear();
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uni_env.interrupts.clear();
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jit.Regs() = regs;
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jit.ExtRegs() = vecs;
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jit.SetFpscr(fpscr);
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jit.SetCpsr(cpsr);
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jit.ClearCache();
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uni.SetRegisters(regs);
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uni.SetExtRegs(vecs);
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uni.SetFpscr(fpscr);
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uni.EnableFloatingPointAccess();
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uni.SetCpsr(cpsr);
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uni.ClearPageCache();
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jit_env.ticks_left = ticks_left;
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jit.Run();
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uni_env.ticks_left = instructions.size(); // Unicorn counts thumb instructions weirdly.
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uni.Run();
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SCOPE_FAIL {
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fmt::print("Instruction Listing:\n");
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fmt::print("{}\n", Common::DisassembleAArch32(std::is_same_v<TestEnv, ThumbTestEnv>, initial_pc, (const u8*)instructions.data(), instructions.size() * sizeof(instructions[0])));
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fmt::print("Initial register listing:\n");
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for (size_t i = 0; i < regs.size(); ++i) {
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fmt::print("{:3s}: {:08x}\n", static_cast<A32::Reg>(i), regs[i]);
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}
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for (size_t i = 0; i < vecs.size(); ++i) {
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fmt::print("{:3s}: {:08x}\n", static_cast<A32::ExtReg>(i), vecs[i]);
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}
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fmt::print("cpsr {:08x}\n", cpsr);
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fmt::print("fpcr {:08x}\n", fpscr);
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fmt::print("fpcr.AHP {}\n", FP::FPCR{fpscr}.AHP());
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fmt::print("fpcr.DN {}\n", FP::FPCR{fpscr}.DN());
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fmt::print("fpcr.FZ {}\n", FP::FPCR{fpscr}.FZ());
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fmt::print("fpcr.RMode {}\n", static_cast<size_t>(FP::FPCR{fpscr}.RMode()));
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fmt::print("fpcr.FZ16 {}\n", FP::FPCR{fpscr}.FZ16());
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fmt::print("\n");
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fmt::print("Final register listing:\n");
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fmt::print(" unicorn dynarmic\n");
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const auto uni_regs = uni.GetRegisters();
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for (size_t i = 0; i < regs.size(); ++i) {
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fmt::print("{:3s}: {:08x} {:08x} {}\n", static_cast<A32::Reg>(i), uni_regs[i], jit.Regs()[i], uni_regs[i] != jit.Regs()[i] ? "*" : "");
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}
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const auto uni_ext_regs = uni.GetExtRegs();
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for (size_t i = 0; i < vecs.size(); ++i) {
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fmt::print("s{:2d}: {:08x} {:08x} {}\n", static_cast<size_t>(i), uni_ext_regs[i], jit.ExtRegs()[i], uni_ext_regs[i] != jit.ExtRegs()[i] ? "*" : "");
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}
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fmt::print("cpsr {:08x} {:08x} {}\n", uni.GetCpsr(), jit.Cpsr(), uni.GetCpsr() != jit.Cpsr() ? "*" : "");
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fmt::print("fpsr {:08x} {:08x} {}\n", uni.GetFpscr(), jit.Fpscr(), (uni.GetFpscr() & 0xF0000000) != (jit.Fpscr() & 0xF0000000) ? "*" : "");
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fmt::print("\n");
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fmt::print("Modified memory:\n");
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fmt::print(" uni dyn\n");
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auto uni_iter = uni_env.modified_memory.begin();
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auto jit_iter = jit_env.modified_memory.begin();
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while (uni_iter != uni_env.modified_memory.end() || jit_iter != jit_env.modified_memory.end()) {
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if (uni_iter == uni_env.modified_memory.end() || (jit_iter != jit_env.modified_memory.end() && uni_iter->first > jit_iter->first)) {
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fmt::print("{:08x}: {:02x} *\n", jit_iter->first, jit_iter->second);
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jit_iter++;
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} else if (jit_iter == jit_env.modified_memory.end() || jit_iter->first > uni_iter->first) {
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fmt::print("{:08x}: {:02x} *\n", uni_iter->first, uni_iter->second);
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uni_iter++;
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} else if (uni_iter->first == jit_iter->first) {
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fmt::print("{:08x}: {:02x} {:02x} {}\n", uni_iter->first, uni_iter->second, jit_iter->second, uni_iter->second != jit_iter->second ? "*" : "");
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uni_iter++;
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jit_iter++;
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}
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}
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fmt::print("\n");
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fmt::print("x86_64:\n");
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fmt::print("{}\n", jit.Disassemble());
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fmt::print("Interrupts:\n");
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for (const auto& i : uni_env.interrupts) {
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std::puts(i.c_str());
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}
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};
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REQUIRE(uni_env.code_mem_modified_by_guest == jit_env.code_mem_modified_by_guest);
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if (uni_env.code_mem_modified_by_guest) {
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return;
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}
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// Qemu doesn't do Thumb transitions??
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{
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const u32 uni_pc = uni.GetPC();
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const bool is_thumb = (jit.Cpsr() & (1 << 5)) != 0;
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const u32 new_uni_pc = uni_pc & (is_thumb ? 0xFFFFFFFE : 0xFFFFFFFC);
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uni.SetPC(new_uni_pc);
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}
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REQUIRE(uni.GetRegisters() == jit.Regs());
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REQUIRE(uni.GetExtRegs() == jit.ExtRegs());
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REQUIRE((uni.GetCpsr() & 0xFFFFFDDF) == (jit.Cpsr() & 0xFFFFFDDF));
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REQUIRE((uni.GetFpscr() & 0xF0000000) == (jit.Fpscr() & 0xF0000000));
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REQUIRE(uni_env.modified_memory == jit_env.modified_memory);
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REQUIRE(uni_env.interrupts.empty());
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}
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} // Anonymous namespace
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TEST_CASE("A32: Single random arm instruction", "[arm]") {
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ArmTestEnv jit_env{};
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ArmTestEnv uni_env{};
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Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
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A32Unicorn<ArmTestEnv> uni{uni_env};
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A32Unicorn<ArmTestEnv>::RegisterArray regs;
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A32Unicorn<ArmTestEnv>::ExtRegArray ext_reg;
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std::vector<u32> instructions(1);
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for (size_t iteration = 0; iteration < 100000; ++iteration) {
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std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
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std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
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instructions[0] = GenRandomArmInst(0, true);
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const u32 start_address = 100;
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const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
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const u32 fpcr = RandomFpcr();
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INFO("Instruction: 0x" << std::hex << instructions[0]);
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regs[15] = start_address;
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RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr, 1);
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}
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}
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TEST_CASE("A32: Small random arm block", "[arm]") {
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ArmTestEnv jit_env{};
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ArmTestEnv uni_env{};
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Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
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A32Unicorn<ArmTestEnv> uni{uni_env};
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A32Unicorn<ArmTestEnv>::RegisterArray regs;
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A32Unicorn<ArmTestEnv>::ExtRegArray ext_reg;
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std::vector<u32> instructions(5);
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for (size_t iteration = 0; iteration < 100000; ++iteration) {
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std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
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std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
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instructions[0] = GenRandomArmInst(0, false);
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instructions[1] = GenRandomArmInst(4, false);
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instructions[2] = GenRandomArmInst(8, false);
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instructions[3] = GenRandomArmInst(12, false);
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instructions[4] = GenRandomArmInst(16, true);
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const u32 start_address = 100;
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const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
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const u32 fpcr = RandomFpcr();
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INFO("Instruction 1: 0x" << std::hex << instructions[0]);
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INFO("Instruction 2: 0x" << std::hex << instructions[1]);
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INFO("Instruction 3: 0x" << std::hex << instructions[2]);
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INFO("Instruction 4: 0x" << std::hex << instructions[3]);
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INFO("Instruction 5: 0x" << std::hex << instructions[4]);
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regs[15] = start_address;
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RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr, 5);
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}
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}
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TEST_CASE("A32: Large random arm block", "[arm]") {
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ArmTestEnv jit_env{};
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ArmTestEnv uni_env{};
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Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
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A32Unicorn<ArmTestEnv> uni{uni_env};
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A32Unicorn<ArmTestEnv>::RegisterArray regs;
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A32Unicorn<ArmTestEnv>::ExtRegArray ext_reg;
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constexpr size_t instruction_count = 100;
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std::vector<u32> instructions(instruction_count);
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for (size_t iteration = 0; iteration < 10000; ++iteration) {
|
|
std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
|
|
for (size_t j = 0; j < instruction_count; ++j) {
|
|
instructions[j] = GenRandomArmInst(j * 4, j == instruction_count - 1);
|
|
}
|
|
|
|
const u64 start_address = 100;
|
|
const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
|
|
const u32 fpcr = RandomFpcr();
|
|
|
|
regs[15] = start_address;
|
|
RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr, 100);
|
|
}
|
|
}
|
|
|
|
TEST_CASE("A32: Single random thumb instruction", "[thumb]") {
|
|
ThumbTestEnv jit_env{};
|
|
ThumbTestEnv uni_env{};
|
|
|
|
Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
|
|
A32Unicorn<ThumbTestEnv> uni{uni_env};
|
|
|
|
A32Unicorn<ThumbTestEnv>::RegisterArray regs;
|
|
A32Unicorn<ThumbTestEnv>::ExtRegArray ext_reg;
|
|
std::vector<u16> instructions;
|
|
|
|
for (size_t iteration = 0; iteration < 100000; ++iteration) {
|
|
std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
|
|
instructions = GenRandomThumbInst(0, true);
|
|
|
|
const u32 start_address = 100;
|
|
const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x1F0;
|
|
const u32 fpcr = RandomFpcr();
|
|
|
|
INFO("Instruction: 0x" << std::hex << instructions[0]);
|
|
|
|
regs[15] = start_address;
|
|
RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr, 1);
|
|
}
|
|
}
|
|
|
|
TEST_CASE("A32: Small random thumb block", "[thumb]") {
|
|
ThumbTestEnv jit_env{};
|
|
ThumbTestEnv uni_env{};
|
|
|
|
Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
|
|
A32Unicorn<ThumbTestEnv> uni{uni_env};
|
|
|
|
A32Unicorn<ThumbTestEnv>::RegisterArray regs;
|
|
A32Unicorn<ThumbTestEnv>::ExtRegArray ext_reg;
|
|
std::vector<u16> instructions;
|
|
|
|
for (size_t iteration = 0; iteration < 100000; ++iteration) {
|
|
std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
|
|
instructions.clear();
|
|
for (size_t i = 0; i < 5; i++) {
|
|
const std::vector<u16> inst = GenRandomThumbInst(instructions.size() * 2, i == 4);
|
|
instructions.insert(instructions.end(), inst.begin(), inst.end());
|
|
}
|
|
|
|
const u32 start_address = 100;
|
|
const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x1F0;
|
|
const u32 fpcr = RandomFpcr();
|
|
|
|
regs[15] = start_address;
|
|
RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr, 5);
|
|
}
|
|
}
|
|
|
|
TEST_CASE("A32: Test thumb IT instruction", "[thumb]") {
|
|
ThumbTestEnv jit_env{};
|
|
ThumbTestEnv uni_env{};
|
|
|
|
Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
|
|
A32Unicorn<ThumbTestEnv> uni{uni_env};
|
|
|
|
A32Unicorn<ThumbTestEnv>::RegisterArray regs;
|
|
A32Unicorn<ThumbTestEnv>::ExtRegArray ext_reg;
|
|
std::vector<u16> instructions;
|
|
|
|
for (size_t iteration = 0; iteration < 100000; ++iteration) {
|
|
std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
|
|
|
const size_t pre_instructions = RandInt<size_t>(0, 3);
|
|
const size_t post_instructions = RandInt<size_t>(5, 8);
|
|
|
|
instructions.clear();
|
|
|
|
for (size_t i = 0; i < pre_instructions; i++) {
|
|
const std::vector<u16> inst = GenRandomThumbInst(instructions.size() * 2, false);
|
|
instructions.insert(instructions.end(), inst.begin(), inst.end());
|
|
}
|
|
|
|
// Emit IT instruction
|
|
A32::ITState it_state = [&]{
|
|
while (true) {
|
|
const u16 imm8 = RandInt<u16>(0, 0xFF);
|
|
if (Common::Bits<0, 3>(imm8) == 0b0000 || Common::Bits<4, 7>(imm8) == 0b1111 || (Common::Bits<4, 7>(imm8) == 0b1110 && Common::BitCount(Common::Bits<0, 3>(imm8)) != 1)) {
|
|
continue;
|
|
}
|
|
instructions.push_back(0b1011111100000000 | imm8);
|
|
return A32::ITState{static_cast<u8>(imm8)};
|
|
}
|
|
}();
|
|
|
|
for (size_t i = 0; i < post_instructions; i++) {
|
|
const std::vector<u16> inst = GenRandomThumbInst(instructions.size() * 2, i == post_instructions - 1, it_state);
|
|
instructions.insert(instructions.end(), inst.begin(), inst.end());
|
|
it_state = it_state.Advance();
|
|
}
|
|
|
|
const u32 start_address = 100;
|
|
const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x1F0;
|
|
const u32 fpcr = RandomFpcr();
|
|
|
|
regs[15] = start_address;
|
|
RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr, pre_instructions + 1 + post_instructions);
|
|
}
|
|
}
|