Lioncash 6b0010c940 ir: Add IR opcodes for emitting vector shuffles ... This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes) as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)		2020-04-22 20:46:15 +01:00
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A32	T32: Add initial decoder list	2020-04-22 20:46:14 +01:00
A64	A64: Implement REV16 (vector)	2020-04-22 20:46:15 +01:00
decoder	General: Convert multiple namespace specifiers to nested namespace specifiers where applicable	2020-04-22 20:44:38 +01:00
ir	ir: Add IR opcodes for emitting vector shuffles	2020-04-22 20:46:15 +01:00