dynarmic/externals/zydis/tests/cases/vexc5_023.out
MerryMage 343b21ff7b externals: Add zydis
Merge commit '6ee9beab3209bc301af98ee881bd15f0aeea2513' as 'externals/zydis'
2021-05-25 21:23:45 +01:00

43 lines
2.3 KiB
Text

== [ BASIC ] ============================================================================================
MNEMONIC: vmulsd [ENC: VEX, MAP: 0F, OPC: 0x59]
LENGTH: 5
SSZ: 64
EOSZ: 32
EASZ: 64
CATEGORY: AVX
ISA-SET: AVX
ISA-EXT: AVX
EXCEPTIONS: AVX3
ATTRIBUTES: HAS_MODRM HAS_SIB HAS_VEX
== [ OPERANDS ] ============================================================================================
## TYPE VISIBILITY ACTION ENCODING SIZE NELEM ELEMSZ ELEMTYPE VALUE
-- --------- ---------- ------ ------------ ---- ----- ------ -------- ---------------------------
0 REGISTER EXPLICIT W MODRM_REG 128 2 64 FLOAT64 xmm0
1 REGISTER EXPLICIT R NDSNDD 128 2 64 FLOAT64 xmm2
2 MEMORY EXPLICIT R MODRM_RM 64 1 64 FLOAT64 TYPE = MEM
SEG = ds
BASE = rcx
INDEX = rdx
SCALE = 1
DISP = 0x0000000000000000
-- --------- ---------- ------ ------------ ---- ----- ------ -------- ---------------------------
== [ AVX ] ============================================================================================
VECTORLEN: 128
BROADCAST: NONE
== [ ATT ] ============================================================================================
ABSOLUTE: vmulsdq (%rcx,%rdx,1), %xmm2, %xmm0
RELATIVE: vmulsdq (%rcx,%rdx,1), %xmm2, %xmm0
== [ INTEL ] ============================================================================================
ABSOLUTE: vmulsd xmm0, xmm2, qword ptr ds:[rcx+rdx*1]
RELATIVE: vmulsd xmm0, xmm2, qword ptr ds:[rcx+rdx*1]
== [ SEGMENTS ] ============================================================================================
C5 EB 59 04 11
: : : :..SIB
: : :..MODRM
: :..OPCODE
:..VEX