343b21ff7b
Merge commit '6ee9beab3209bc301af98ee881bd15f0aeea2513' as 'externals/zydis'
43 lines
2.3 KiB
Text
43 lines
2.3 KiB
Text
== [ BASIC ] ============================================================================================
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MNEMONIC: vmulsd [ENC: VEX, MAP: 0F, OPC: 0x59]
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LENGTH: 5
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SSZ: 64
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EOSZ: 32
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EASZ: 64
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CATEGORY: AVX
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ISA-SET: AVX
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ISA-EXT: AVX
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EXCEPTIONS: AVX3
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ATTRIBUTES: HAS_MODRM HAS_SIB HAS_VEX
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== [ OPERANDS ] ============================================================================================
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## TYPE VISIBILITY ACTION ENCODING SIZE NELEM ELEMSZ ELEMTYPE VALUE
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-- --------- ---------- ------ ------------ ---- ----- ------ -------- ---------------------------
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0 REGISTER EXPLICIT W MODRM_REG 128 2 64 FLOAT64 xmm0
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1 REGISTER EXPLICIT R NDSNDD 128 2 64 FLOAT64 xmm2
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2 MEMORY EXPLICIT R MODRM_RM 64 1 64 FLOAT64 TYPE = MEM
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SEG = ds
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BASE = rcx
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INDEX = rdx
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SCALE = 1
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DISP = 0x0000000000000000
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-- --------- ---------- ------ ------------ ---- ----- ------ -------- ---------------------------
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== [ AVX ] ============================================================================================
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VECTORLEN: 128
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BROADCAST: NONE
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== [ ATT ] ============================================================================================
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ABSOLUTE: vmulsdq (%rcx,%rdx,1), %xmm2, %xmm0
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RELATIVE: vmulsdq (%rcx,%rdx,1), %xmm2, %xmm0
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== [ INTEL ] ============================================================================================
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ABSOLUTE: vmulsd xmm0, xmm2, qword ptr ds:[rcx+rdx*1]
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RELATIVE: vmulsd xmm0, xmm2, qword ptr ds:[rcx+rdx*1]
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== [ SEGMENTS ] ============================================================================================
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C5 EB 59 04 11
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: : : :..SIB
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: : :..MODRM
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: :..OPCODE
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:..VEX
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