320 lines
9.4 KiB
C++
320 lines
9.4 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <unordered_map>
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#include "backend_x64/block_of_code.h"
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#include "backend_x64/emit_x64.h"
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/variant_util.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/opcodes.h"
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// TODO: Have ARM flags in host flags and not have them use up GPR registers unless necessary.
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// TODO: Actually implement that proper instruction selector you've always wanted to sweetheart.
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namespace Dynarmic::BackendX64 {
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using namespace Xbyak::util;
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EmitContext::EmitContext(RegAlloc& reg_alloc, IR::Block& block)
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: reg_alloc(reg_alloc), block(block) {}
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void EmitContext::EraseInstruction(IR::Inst* inst) {
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block.Instructions().erase(inst);
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inst->ClearArgs();
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}
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EmitX64::EmitX64(BlockOfCode* code)
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: code(code) {}
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EmitX64::~EmitX64() = default;
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boost::optional<typename EmitX64::BlockDescriptor> EmitX64::GetBasicBlock(IR::LocationDescriptor descriptor) const {
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auto iter = block_descriptors.find(descriptor);
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if (iter == block_descriptors.end())
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return boost::none;
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return iter->second;
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}
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void EmitX64::EmitVoid(EmitContext&, IR::Inst*) {
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}
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void EmitX64::EmitBreakpoint(EmitContext&, IR::Inst*) {
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code->int3();
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}
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void EmitX64::EmitIdentity(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (!args[0].IsImmediate()) {
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ctx.reg_alloc.DefineValue(inst, args[0]);
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}
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}
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void EmitX64::PushRSBHelper(Xbyak::Reg64 loc_desc_reg, Xbyak::Reg64 index_reg, IR::LocationDescriptor target) {
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using namespace Xbyak::util;
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auto iter = block_descriptors.find(target);
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CodePtr target_code_ptr = iter != block_descriptors.end()
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? iter->second.entrypoint
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: code->GetReturnFromRunCodeAddress();
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code->mov(index_reg.cvt32(), dword[r15 + code->GetJitStateInfo().offsetof_rsb_ptr]);
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code->mov(loc_desc_reg, target.Value());
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patch_information[target].mov_rcx.emplace_back(code->getCurr());
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EmitPatchMovRcx(target_code_ptr);
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code->mov(qword[r15 + index_reg * 8 + code->GetJitStateInfo().offsetof_rsb_location_descriptors], loc_desc_reg);
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code->mov(qword[r15 + index_reg * 8 + code->GetJitStateInfo().offsetof_rsb_codeptrs], rcx);
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code->add(index_reg.cvt32(), 1);
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code->and_(index_reg.cvt32(), u32(code->GetJitStateInfo().rsb_ptr_mask));
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code->mov(dword[r15 + code->GetJitStateInfo().offsetof_rsb_ptr], index_reg.cvt32());
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}
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void EmitX64::EmitPushRSB(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ASSERT(args[0].IsImmediate());
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u64 unique_hash_of_target = args[0].GetImmediateU64();
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ctx.reg_alloc.ScratchGpr({HostLoc::RCX});
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Xbyak::Reg64 loc_desc_reg = ctx.reg_alloc.ScratchGpr();
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Xbyak::Reg64 index_reg = ctx.reg_alloc.ScratchGpr();
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PushRSBHelper(loc_desc_reg, index_reg, IR::LocationDescriptor{unique_hash_of_target});
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}
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void EmitX64::EmitGetCarryFromOp(EmitContext&, IR::Inst*) {
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ASSERT_MSG(false, "should never happen");
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}
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void EmitX64::EmitGetOverflowFromOp(EmitContext&, IR::Inst*) {
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ASSERT_MSG(false, "should never happen");
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}
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void EmitX64::EmitGetGEFromOp(EmitContext&, IR::Inst*) {
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ASSERT_MSG(false, "should never happen");
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}
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void EmitX64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const int bitsize = [&]{
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switch (args[0].GetType()) {
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case IR::Type::U8:
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return 8;
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case IR::Type::U16:
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return 16;
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case IR::Type::U32:
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return 32;
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case IR::Type::U64:
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return 64;
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default:
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ASSERT_MSG(false, "Unreachable");
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return 0;
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}
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}();
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Xbyak::Reg64 nzcv = ctx.reg_alloc.ScratchGpr({HostLoc::RAX});
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Xbyak::Reg value = ctx.reg_alloc.UseGpr(args[0]).changeBit(bitsize);
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code->cmp(value, 0);
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code->lahf();
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code->seto(code->al);
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ctx.reg_alloc.DefineValue(inst, nzcv);
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}
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void EmitX64::EmitAddCycles(size_t cycles) {
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ASSERT(cycles < std::numeric_limits<u32>::max());
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code->sub(qword[r15 + code->GetJitStateInfo().offsetof_cycles_remaining], static_cast<u32>(cycles));
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}
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Xbyak::Label EmitX64::EmitCond(IR::Cond cond) {
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Xbyak::Label label;
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const Xbyak::Reg32 cpsr = eax;
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code->mov(cpsr, dword[r15 + code->GetJitStateInfo().offsetof_CPSR_nzcv]);
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constexpr size_t n_shift = 31;
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constexpr size_t z_shift = 30;
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constexpr size_t c_shift = 29;
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constexpr size_t v_shift = 28;
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constexpr u32 n_mask = 1u << n_shift;
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constexpr u32 z_mask = 1u << z_shift;
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constexpr u32 c_mask = 1u << c_shift;
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constexpr u32 v_mask = 1u << v_shift;
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switch (cond) {
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case IR::Cond::EQ: //z
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code->test(cpsr, z_mask);
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code->jnz(label);
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break;
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case IR::Cond::NE: //!z
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code->test(cpsr, z_mask);
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code->jz(label);
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break;
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case IR::Cond::CS: //c
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code->test(cpsr, c_mask);
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code->jnz(label);
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break;
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case IR::Cond::CC: //!c
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code->test(cpsr, c_mask);
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code->jz(label);
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break;
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case IR::Cond::MI: //n
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code->test(cpsr, n_mask);
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code->jnz(label);
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break;
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case IR::Cond::PL: //!n
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code->test(cpsr, n_mask);
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code->jz(label);
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break;
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case IR::Cond::VS: //v
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code->test(cpsr, v_mask);
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code->jnz(label);
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break;
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case IR::Cond::VC: //!v
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code->test(cpsr, v_mask);
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code->jz(label);
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break;
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case IR::Cond::HI: { //c & !z
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code->and_(cpsr, z_mask | c_mask);
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code->cmp(cpsr, c_mask);
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code->je(label);
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break;
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}
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case IR::Cond::LS: { //!c | z
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code->and_(cpsr, z_mask | c_mask);
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code->cmp(cpsr, c_mask);
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code->jne(label);
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break;
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}
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case IR::Cond::GE: { // n == v
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code->and_(cpsr, n_mask | v_mask);
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code->jz(label);
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code->cmp(cpsr, n_mask | v_mask);
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code->je(label);
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break;
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}
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case IR::Cond::LT: { // n != v
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Xbyak::Label fail;
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code->and_(cpsr, n_mask | v_mask);
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code->jz(fail);
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code->cmp(cpsr, n_mask | v_mask);
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code->jne(label);
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code->L(fail);
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break;
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}
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case IR::Cond::GT: { // !z & (n == v)
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const Xbyak::Reg32 tmp1 = ebx;
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const Xbyak::Reg32 tmp2 = esi;
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code->mov(tmp1, cpsr);
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code->mov(tmp2, cpsr);
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code->shr(tmp1, n_shift);
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code->shr(tmp2, v_shift);
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code->shr(cpsr, z_shift);
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code->xor_(tmp1, tmp2);
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code->or_(tmp1, cpsr);
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code->test(tmp1, 1);
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code->jz(label);
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break;
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}
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case IR::Cond::LE: { // z | (n != v)
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const Xbyak::Reg32 tmp1 = ebx;
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const Xbyak::Reg32 tmp2 = esi;
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code->mov(tmp1, cpsr);
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code->mov(tmp2, cpsr);
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code->shr(tmp1, n_shift);
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code->shr(tmp2, v_shift);
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code->shr(cpsr, z_shift);
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code->xor_(tmp1, tmp2);
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code->or_(tmp1, cpsr);
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code->test(tmp1, 1);
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code->jnz(label);
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break;
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}
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default:
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ASSERT_MSG(false, "Unknown cond %zu", static_cast<size_t>(cond));
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break;
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}
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return label;
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}
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void EmitX64::EmitCondPrelude(const IR::Block& block) {
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if (block.GetCondition() == IR::Cond::AL) {
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ASSERT(!block.HasConditionFailedLocation());
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return;
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}
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ASSERT(block.HasConditionFailedLocation());
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Xbyak::Label pass = EmitCond(block.GetCondition());
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EmitAddCycles(block.ConditionFailedCycleCount());
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EmitTerminal(IR::Term::LinkBlock{block.ConditionFailedLocation()}, block.Location());
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code->L(pass);
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}
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void EmitX64::EmitTerminal(IR::Terminal terminal, IR::LocationDescriptor initial_location) {
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Common::VisitVariant<void>(terminal, [this, &initial_location](auto x) {
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using T = std::decay_t<decltype(x)>;
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if constexpr (!std::is_same_v<T, IR::Term::Invalid>) {
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this->EmitTerminalImpl(x, initial_location);
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} else {
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ASSERT_MSG(false, "Invalid terminal");
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}
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});
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}
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void EmitX64::Patch(const IR::LocationDescriptor& desc, CodePtr bb) {
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const CodePtr save_code_ptr = code->getCurr();
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const PatchInformation& patch_info = patch_information[desc];
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for (CodePtr location : patch_info.jg) {
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code->SetCodePtr(location);
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EmitPatchJg(desc, bb);
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}
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for (CodePtr location : patch_info.jmp) {
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code->SetCodePtr(location);
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EmitPatchJmp(desc, bb);
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}
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for (CodePtr location : patch_info.mov_rcx) {
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code->SetCodePtr(location);
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EmitPatchMovRcx(bb);
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}
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code->SetCodePtr(save_code_ptr);
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}
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void EmitX64::Unpatch(const IR::LocationDescriptor& desc) {
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Patch(desc, nullptr);
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}
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void EmitX64::ClearCache() {
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block_descriptors.clear();
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patch_information.clear();
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}
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void EmitX64::InvalidateBasicBlocks(const std::unordered_set<IR::LocationDescriptor>& locations) {
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for (const auto &descriptor : locations) {
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auto it = block_descriptors.find(descriptor);
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if (it == block_descriptors.end()) {
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continue;
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}
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if (patch_information.count(descriptor)) {
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Unpatch(descriptor);
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}
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block_descriptors.erase(it);
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}
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}
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} // namespace Dynarmic::BackendX64
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