424 lines
15 KiB
C++
424 lines
15 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include <cstring>
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#include <string>
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#include <vector>
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#include <catch.hpp>
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#include "common/fp/fpsr.h"
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#include "common/llvm_disassemble.h"
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#include "common/scope_exit.h"
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#include "frontend/A64/decoder/a64.h"
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#include "frontend/A64/location_descriptor.h"
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#include "frontend/A64/translate/translate.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/opcodes.h"
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#include "inst_gen.h"
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#include "rand_int.h"
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#include "testenv.h"
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#include "unicorn_emu/unicorn.h"
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// Needs to be declaerd before <fmt/ostream.h>
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static std::ostream& operator<<(std::ostream& o, const Dynarmic::A64::Vector& vec) {
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return o << fmt::format("{:016x}'{:016x}", vec[1], vec[0]);
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}
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#include <fmt/format.h>
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#include <fmt/ostream.h>
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using namespace Dynarmic;
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static Vector RandomVector() {
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return {RandInt<u64>(0, ~u64(0)), RandInt<u64>(0, ~u64(0))};
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}
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static bool ShouldTestInst(u32 instruction, u64 pc, bool is_last_inst) {
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const A64::LocationDescriptor location{pc, {}};
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IR::Block block{location};
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bool should_continue = A64::TranslateSingleInstruction(block, location, instruction);
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if (!should_continue && !is_last_inst)
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return false;
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if (auto terminal = block.GetTerminal(); boost::get<IR::Term::Interpret>(&terminal))
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return false;
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for (const auto& ir_inst : block) {
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switch (ir_inst.GetOpcode()) {
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case IR::Opcode::A64ExceptionRaised:
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case IR::Opcode::A64CallSupervisor:
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case IR::Opcode::A64DataCacheOperationRaised:
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case IR::Opcode::A64GetCNTPCT:
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return false;
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default:
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continue;
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}
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}
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return true;
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}
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static u32 GenRandomInst(u64 pc, bool is_last_inst) {
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static const std::vector<InstructionGenerator> instruction_generators = []{
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const std::vector<std::tuple<std::string, const char*>> list {
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#define INST(fn, name, bitstring) {#fn, bitstring},
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#include "frontend/A64/decoder/a64.inc"
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#undef INST
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};
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std::vector<InstructionGenerator> result;
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// List of instructions not to test
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const std::vector<std::string> do_not_test {
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// Unimplemented in QEMU
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"STLLR",
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// Unimplemented in QEMU
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"LDLAR",
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// Dynarmic and QEMU currently differ on how the exclusive monitor's address range works.
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"STXR", "STLXR", "STXP", "STLXP", "LDXR", "LDAXR", "LDXP", "LDAXP",
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// QEMU's implementation of FDIV is incorrect
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"FDIV_1", "FDIV_2",
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};
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for (const auto& [fn, bitstring] : list) {
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if (fn == "UnallocatedEncoding") {
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continue;
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}
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if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
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InstructionGenerator::AddInvalidInstruction(bitstring);
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continue;
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}
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result.emplace_back(InstructionGenerator{bitstring});
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}
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return result;
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}();
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while (true) {
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const size_t index = RandInt<size_t>(0, instruction_generators.size() - 1);
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const u32 instruction = instruction_generators[index].Generate();
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if (ShouldTestInst(instruction, pc, is_last_inst)) {
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return instruction;
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}
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}
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}
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static u32 GenFloatInst(u64 pc, bool is_last_inst) {
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static const std::vector<InstructionGenerator> instruction_generators = []{
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const std::vector<std::tuple<std::string, std::string, const char*>> list {
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#define INST(fn, name, bitstring) {#fn, #name, bitstring},
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#include "frontend/A64/decoder/a64.inc"
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#undef INST
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};
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// List of instructions not to test
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const std::vector<std::string> do_not_test {
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// QEMU's implementation of FCVT is incorrect
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"FCVT_float",
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// QEMU's implementation of FDIV is incorrect
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"FDIV_1", "FDIV_2",
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};
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std::vector<InstructionGenerator> result;
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for (const auto& [fn, name, bitstring] : list) {
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(void)name;
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if (fn[0] != 'F') {
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continue;
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} else if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
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continue;
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}
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result.emplace_back(InstructionGenerator{bitstring});
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}
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return result;
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}();
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while (true) {
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const size_t index = RandInt<size_t>(0, instruction_generators.size() - 1);
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const u32 instruction = instruction_generators[index].Generate();
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if ((instruction & 0x00800000) == 0 && ShouldTestInst(instruction, pc, is_last_inst)) {
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return instruction;
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}
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}
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}
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static void RunTestInstance(const Unicorn::RegisterArray& regs, const Unicorn::VectorArray& vecs, const size_t instructions_offset,
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const std::vector<u32>& instructions, const u32 pstate, const u32 fpcr) {
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static TestEnv jit_env{};
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static TestEnv uni_env{};
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std::copy(instructions.begin(), instructions.end(), jit_env.code_mem.begin() + instructions_offset);
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std::copy(instructions.begin(), instructions.end(), uni_env.code_mem.begin() + instructions_offset);
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jit_env.code_mem[instructions.size() + instructions_offset] = 0x14000000; // B .
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uni_env.code_mem[instructions.size() + instructions_offset] = 0x14000000; // B .
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jit_env.modified_memory.clear();
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uni_env.modified_memory.clear();
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jit_env.interrupts.clear();
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uni_env.interrupts.clear();
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Dynarmic::A64::UserConfig jit_user_config{&jit_env};
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// The below corresponds to the settings for qemu's aarch64_max_initfn
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jit_user_config.dczid_el0 = 7;
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jit_user_config.ctr_el0 = 0x80038003;
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static Dynarmic::A64::Jit jit{jit_user_config};
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static Unicorn uni{uni_env};
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jit.SetRegisters(regs);
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jit.SetVectors(vecs);
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jit.SetPC(instructions_offset * 4);
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jit.SetSP(0x08000000);
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jit.SetFpcr(fpcr);
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jit.SetFpsr(0);
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jit.SetPstate(pstate);
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jit.ClearCache();
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uni.SetRegisters(regs);
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uni.SetVectors(vecs);
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uni.SetPC(instructions_offset * 4);
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uni.SetSP(0x08000000);
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uni.SetFpcr(fpcr);
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uni.SetFpsr(0);
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uni.SetPstate(pstate);
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uni.ClearPageCache();
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jit_env.ticks_left = instructions.size();
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jit.Run();
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uni_env.ticks_left = instructions.size();
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uni.Run();
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SCOPE_FAIL {
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fmt::print("Instruction Listing:\n");
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for (u32 instruction : instructions)
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fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch64(instruction));
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fmt::print("\n");
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fmt::print("Initial register listing:\n");
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for (size_t i = 0; i < regs.size(); ++i)
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fmt::print("{:3s}: {:016x}\n", static_cast<A64::Reg>(i), regs[i]);
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for (size_t i = 0; i < vecs.size(); ++i)
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fmt::print("{:3s}: {}\n", static_cast<A64::Vec>(i), vecs[i]);
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fmt::print("sp : 08000000\n");
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fmt::print("pc : {:016x}\n", instructions_offset * 4);
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fmt::print("p : {:08x}\n", pstate);
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fmt::print("fpcr {:08x}\n", fpcr);
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fmt::print("\n");
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fmt::print("Final register listing:\n");
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fmt::print(" unicorn dynarmic\n");
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for (size_t i = 0; i < regs.size(); ++i)
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fmt::print("{:3s}: {:016x} {:016x} {}\n", static_cast<A64::Reg>(i), uni.GetRegisters()[i], jit.GetRegisters()[i], uni.GetRegisters()[i] != jit.GetRegisters()[i] ? "*" : "");
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for (size_t i = 0; i < vecs.size(); ++i)
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fmt::print("{:3s}: {} {} {}\n", static_cast<A64::Vec>(i), uni.GetVectors()[i], jit.GetVectors()[i], uni.GetVectors()[i] != jit.GetVectors()[i] ? "*" : "");
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fmt::print("sp : {:016x} {:016x} {}\n", uni.GetSP(), jit.GetSP(), uni.GetSP() != jit.GetSP() ? "*" : "");
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fmt::print("pc : {:016x} {:016x} {}\n", uni.GetPC(), jit.GetPC(), uni.GetPC() != jit.GetPC() ? "*" : "");
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fmt::print("p : {:08x} {:08x} {}\n", uni.GetPstate(), jit.GetPstate(), (uni.GetPstate() & 0xF0000000) != (jit.GetPstate() & 0xF0000000) ? "*" : "");
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fmt::print("qc : {:08x} {:08x} {}\n", uni.GetFpsr(), jit.GetFpsr(), FP::FPSR{uni.GetFpsr()}.QC() != FP::FPSR{jit.GetFpsr()}.QC() ? "*" : "");
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fmt::print("\n");
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fmt::print("Modified memory:\n");
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fmt::print(" uni dyn\n");
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auto uni_iter = uni_env.modified_memory.begin();
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auto jit_iter = jit_env.modified_memory.begin();
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while (uni_iter != uni_env.modified_memory.end() || jit_iter != jit_env.modified_memory.end()) {
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if (uni_iter == uni_env.modified_memory.end() || (jit_iter != jit_env.modified_memory.end() && uni_iter->first > jit_iter->first)) {
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fmt::print("{:016x}: {:02x} *\n", jit_iter->first, jit_iter->second);
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jit_iter++;
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} else if (jit_iter == jit_env.modified_memory.end() || jit_iter->first > uni_iter->first) {
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fmt::print("{:016x}: {:02x} *\n", uni_iter->first, uni_iter->second);
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uni_iter++;
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} else if (uni_iter->first == jit_iter->first) {
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fmt::print("{:016x}: {:02x} {:02x} {}\n", uni_iter->first, uni_iter->second, jit_iter->second, uni_iter->second != jit_iter->second ? "*" : "");
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uni_iter++;
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jit_iter++;
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}
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}
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fmt::print("\n");
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fmt::print("x86_64:\n");
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fmt::print("{}\n", jit.Disassemble());
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fmt::print("Interrupts:\n");
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for (auto& i : uni_env.interrupts) {
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puts(i.c_str());
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}
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};
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REQUIRE(uni_env.code_mem_modified_by_guest == jit_env.code_mem_modified_by_guest);
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if (uni_env.code_mem_modified_by_guest) {
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return;
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}
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REQUIRE(uni.GetPC() == jit.GetPC());
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REQUIRE(uni.GetRegisters() == jit.GetRegisters());
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REQUIRE(uni.GetVectors() == jit.GetVectors());
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REQUIRE(uni.GetSP() == jit.GetSP());
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REQUIRE((uni.GetPstate() & 0xF0000000) == (jit.GetPstate() & 0xF0000000));
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REQUIRE(uni_env.modified_memory == jit_env.modified_memory);
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REQUIRE(uni_env.interrupts.empty());
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REQUIRE(FP::FPSR{uni.GetFpsr()}.QC() == FP::FPSR{jit.GetFpsr()}.QC());
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}
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TEST_CASE("A64: Single random instruction", "[a64]") {
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Unicorn::RegisterArray regs;
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Unicorn::VectorArray vecs;
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std::vector<u32> instructions(1);
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for (size_t iteration = 0; iteration < 100000; ++iteration) {
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std::generate(regs.begin(), regs.end(), []{ return RandInt<u64>(0, ~u64(0)); });
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std::generate(vecs.begin(), vecs.end(), RandomVector);
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instructions[0] = GenRandomInst(0, true);
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u32 pstate = RandInt<u32>(0, 0xF) << 28;
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u32 fpcr = RandInt<u32>(0, 0x3) << 22; // randomize RMode
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INFO("Instruction: 0x" << std::hex << instructions[0]);
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RunTestInstance(regs, vecs, 100, instructions, pstate, fpcr);
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}
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}
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TEST_CASE("A64: Floating point instructions", "[a64]") {
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static constexpr std::array<u64, 80> float_numbers {
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0x00000000, // positive zero
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0x00000001, // smallest positive denormal
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0x00000076, //
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0x00002b94, //
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0x00636d24, //
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0x007fffff, // largest positive denormal
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0x00800000, // smallest positive normalised real
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0x00800002, //
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0x01398437, //
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0x0ba98d27, //
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0x0ba98d7a, //
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0x751f853a, //
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0x7f7ffff0, //
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0x7f7fffff, // largest positive normalised real
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0x7f800000, // positive infinity
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0x7f800001, // first positive SNaN
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0x7f984a37, //
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0x7fbfffff, // last positive SNaN
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0x7fc00000, // first positive QNaN
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0x7fd9ba98, //
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0x7fffffff, // last positive QNaN
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0x80000000, // negative zero
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0x80000001, // smallest negative denormal
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0x80000076, //
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0x80002b94, //
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0x80636d24, //
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0x807fffff, // largest negative denormal
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0x80800000, // smallest negative normalised real
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0x80800002, //
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0x81398437, //
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0x8ba98d27, //
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0x8ba98d7a, //
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0xf51f853a, //
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0xff7ffff0, //
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0xff7fffff, // largest negative normalised real
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0xff800000, // negative infinity
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0xff800001, // first negative SNaN
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0xff984a37, //
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0xffbfffff, // last negative SNaN
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0xffc00000, // first negative QNaN
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0xffd9ba98, //
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0xffffffff, // last negative QNaN
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// some random numbers follow
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0x4f3495cb,
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0xe73a5134,
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0x7c994e9e,
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0x6164bd6c,
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0x09503366,
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0xbf5a97c9,
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0xe6ff1a14,
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0x77f31e2f,
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0xaab4d7d8,
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0x0966320b,
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0xb26bddee,
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0xb5c8e5d3,
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0x317285d3,
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0x3c9623b1,
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0x51fd2c7c,
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0x7b906a6c,
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0x3f800000,
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0x3dcccccd,
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0x3f000000,
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0x42280000,
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0x3eaaaaab,
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0xc1200000,
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0xbf800000,
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0xbf8147ae,
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0x3f8147ae,
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0x415df525,
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0xc79b271e,
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0x460e8c84,
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// some 64-bit-float upper-halves
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0x7ff00000, // +SNaN / +Inf
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0x7ff0abcd, // +SNaN
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0x7ff80000, // +QNaN
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0x7ff81234, // +QNaN
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0xfff00000, // -SNaN / -Inf
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0xfff05678, // -SNaN
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0xfff80000, // -QNaN
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0xfff809ef, // -QNaN
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0x3ff00000, // Number near +1.0
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0xbff00000, // Number near -1.0
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};
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const auto gen_float = [&]{
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return float_numbers[RandInt<size_t>(0, float_numbers.size() - 1)];
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};
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const auto gen_vector = [&]{
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u64 upper = (gen_float() << 32) | gen_float();
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u64 lower = (gen_float() << 32) | gen_float();
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return Vector{lower, upper};
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};
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Unicorn::RegisterArray regs;
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Unicorn::VectorArray vecs;
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std::vector<u32> instructions(1);
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for (size_t iteration = 0; iteration < 100000; ++iteration) {
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std::generate(regs.begin(), regs.end(), gen_float);
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std::generate(vecs.begin(), vecs.end(), gen_vector);
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instructions[0] = GenFloatInst(0, true);
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u32 pstate = RandInt<u32>(0, 0xF) << 28;
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u32 fpcr = RandInt<u32>(0, 0x3) << 22; // randomize RMode
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INFO("Instruction: 0x" << std::hex << instructions[0]);
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RunTestInstance(regs, vecs, 100, instructions, pstate, fpcr);
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}
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}
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TEST_CASE("A64: Small random block", "[a64]") {
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Unicorn::RegisterArray regs;
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Unicorn::VectorArray vecs;
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std::vector<u32> instructions(5);
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for (size_t iteration = 0; iteration < 100000; ++iteration) {
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std::generate(regs.begin(), regs.end(), [] { return RandInt<u64>(0, ~u64(0)); });
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std::generate(vecs.begin(), vecs.end(), RandomVector);
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instructions[0] = GenRandomInst(0, false);
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instructions[1] = GenRandomInst(4, false);
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instructions[2] = GenRandomInst(8, false);
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instructions[3] = GenRandomInst(12, false);
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instructions[4] = GenRandomInst(16, true);
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u32 pstate = RandInt<u32>(0, 0xF) << 28;
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u32 fpcr = RandInt<u32>(0, 0x3) << 22; // randomize RMode
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INFO("Instruction 1: 0x" << std::hex << instructions[0]);
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INFO("Instruction 2: 0x" << std::hex << instructions[1]);
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INFO("Instruction 3: 0x" << std::hex << instructions[2]);
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INFO("Instruction 4: 0x" << std::hex << instructions[3]);
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INFO("Instruction 5: 0x" << std::hex << instructions[4]);
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RunTestInstance(regs, vecs, 100, instructions, pstate, fpcr);
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}
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}
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