1072 lines
36 KiB
C++
1072 lines
36 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <type_traits>
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#include "backend_x64/abi.h"
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#include "backend_x64/block_of_code.h"
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#include "backend_x64/emit_x64.h"
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/fp_util.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/opcodes.h"
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namespace Dynarmic::BackendX64 {
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using namespace Xbyak::util;
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constexpr u64 f32_negative_zero = 0x80000000u;
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constexpr u64 f32_nan = 0x7fc00000u;
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constexpr u64 f32_non_sign_mask = 0x7fffffffu;
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constexpr u64 f64_negative_zero = 0x8000000000000000u;
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constexpr u64 f64_nan = 0x7ff8000000000000u;
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constexpr u64 f64_non_sign_mask = 0x7fffffffffffffffu;
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constexpr u64 f64_penultimate_positive_denormal = 0x000ffffffffffffeu;
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constexpr u64 f64_min_s32 = 0xc1e0000000000000u; // -2147483648 as a double
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constexpr u64 f64_max_s32 = 0x41dfffffffc00000u; // 2147483647 as a double
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constexpr u64 f64_min_u32 = 0x0000000000000000u; // 0 as a double
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constexpr u64 f64_max_u32 = 0x41efffffffe00000u; // 4294967295 as a double
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static void DenormalsAreZero32(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Reg32 gpr_scratch) {
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Xbyak::Label end;
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// We need to report back whether we've found a denormal on input.
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// SSE doesn't do this for us when SSE's DAZ is enabled.
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code.movd(gpr_scratch, xmm_value);
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code.and_(gpr_scratch, u32(0x7FFFFFFF));
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code.sub(gpr_scratch, u32(1));
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code.cmp(gpr_scratch, u32(0x007FFFFE));
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code.ja(end);
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code.pxor(xmm_value, xmm_value);
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code.mov(dword[r15 + code.GetJitStateInfo().offsetof_FPSCR_IDC], u32(1 << 7));
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code.L(end);
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}
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static void DenormalsAreZero64(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Reg64 gpr_scratch) {
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Xbyak::Label end;
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auto mask = code.MConst(xword, f64_non_sign_mask);
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mask.setBit(64);
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auto penult_denormal = code.MConst(xword, f64_penultimate_positive_denormal);
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penult_denormal.setBit(64);
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code.movq(gpr_scratch, xmm_value);
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code.and_(gpr_scratch, mask);
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code.sub(gpr_scratch, u32(1));
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code.cmp(gpr_scratch, penult_denormal);
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code.ja(end);
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code.pxor(xmm_value, xmm_value);
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code.mov(dword[r15 + code.GetJitStateInfo().offsetof_FPSCR_IDC], u32(1 << 7));
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code.L(end);
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}
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static void FlushToZero32(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Reg32 gpr_scratch) {
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Xbyak::Label end;
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code.movd(gpr_scratch, xmm_value);
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code.and_(gpr_scratch, u32(0x7FFFFFFF));
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code.sub(gpr_scratch, u32(1));
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code.cmp(gpr_scratch, u32(0x007FFFFE));
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code.ja(end);
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code.pxor(xmm_value, xmm_value);
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code.mov(dword[r15 + code.GetJitStateInfo().offsetof_FPSCR_UFC], u32(1 << 3));
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code.L(end);
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}
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static void FlushToZero64(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Reg64 gpr_scratch) {
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Xbyak::Label end;
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auto mask = code.MConst(xword, f64_non_sign_mask);
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mask.setBit(64);
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auto penult_denormal = code.MConst(xword, f64_penultimate_positive_denormal);
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penult_denormal.setBit(64);
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code.movq(gpr_scratch, xmm_value);
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code.and_(gpr_scratch, mask);
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code.sub(gpr_scratch, u32(1));
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code.cmp(gpr_scratch, penult_denormal);
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code.ja(end);
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code.pxor(xmm_value, xmm_value);
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code.mov(dword[r15 + code.GetJitStateInfo().offsetof_FPSCR_UFC], u32(1 << 3));
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code.L(end);
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}
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static void ZeroIfNaN64(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Xmm xmm_scratch) {
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code.pxor(xmm_scratch, xmm_scratch);
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code.cmpordsd(xmm_scratch, xmm_value); // true mask when ordered (i.e.: when not an NaN)
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code.pand(xmm_value, xmm_scratch);
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}
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static void PreProcessNaNs32(BlockOfCode& code, Xbyak::Xmm a, Xbyak::Xmm b, Xbyak::Label& end) {
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Xbyak::Label nan;
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code.ucomiss(a, b);
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code.jp(nan, code.T_NEAR);
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code.SwitchToFarCode();
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code.L(nan);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.xor_(code.ABI_PARAM1.cvt32(), code.ABI_PARAM1.cvt32());
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code.xor_(code.ABI_PARAM2.cvt32(), code.ABI_PARAM2.cvt32());
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code.movd(code.ABI_PARAM1.cvt32(), a);
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code.movd(code.ABI_PARAM2.cvt32(), b);
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code.CallFunction(static_cast<u32(*)(u32, u32)>([](u32 a, u32 b) -> u32 {
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return *Common::ProcessNaNs(a, b);
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}));
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code.movd(a, code.ABI_RETURN.cvt32());
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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}
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static void PreProcessNaNs32(BlockOfCode& code, Xbyak::Xmm a, Xbyak::Xmm b, Xbyak::Xmm c, Xbyak::Label& end) {
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Xbyak::Label nan;
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code.ucomiss(a, b);
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code.jp(nan, code.T_NEAR);
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code.ucomiss(c, c);
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code.jp(nan, code.T_NEAR);
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code.SwitchToFarCode();
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code.L(nan);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.xor_(code.ABI_PARAM1.cvt32(), code.ABI_PARAM1.cvt32());
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code.xor_(code.ABI_PARAM2.cvt32(), code.ABI_PARAM2.cvt32());
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code.xor_(code.ABI_PARAM3.cvt32(), code.ABI_PARAM3.cvt32());
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code.movd(code.ABI_PARAM1.cvt32(), a);
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code.movd(code.ABI_PARAM2.cvt32(), b);
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code.movd(code.ABI_PARAM3.cvt32(), c);
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code.CallFunction(static_cast<u32(*)(u32, u32, u32)>([](u32 a, u32 b, u32 c) -> u32 {
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return *Common::ProcessNaNs(a, b, c);
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}));
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code.movd(a, code.ABI_RETURN.cvt32());
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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}
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static void PostProcessNaNs32(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm tmp) {
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code.movaps(tmp, result);
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code.cmpunordps(tmp, tmp);
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code.pslld(tmp, 31);
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code.xorps(result, tmp);
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}
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static void DefaultNaN32(BlockOfCode& code, Xbyak::Xmm xmm_value) {
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Xbyak::Label end;
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code.ucomiss(xmm_value, xmm_value);
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code.jnp(end);
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code.movaps(xmm_value, code.MConst(xword, f32_nan));
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code.L(end);
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}
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static void PreProcessNaNs64(BlockOfCode& code, Xbyak::Xmm a, Xbyak::Xmm b, Xbyak::Label& end) {
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Xbyak::Label nan;
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code.ucomisd(a, b);
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code.jp(nan, code.T_NEAR);
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code.SwitchToFarCode();
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code.L(nan);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.movq(code.ABI_PARAM1, a);
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code.movq(code.ABI_PARAM2, b);
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code.CallFunction(static_cast<u64(*)(u64, u64)>([](u64 a, u64 b) -> u64 {
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return *Common::ProcessNaNs(a, b);
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}));
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code.movq(a, code.ABI_RETURN);
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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}
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static void PreProcessNaNs64(BlockOfCode& code, Xbyak::Xmm a, Xbyak::Xmm b, Xbyak::Xmm c, Xbyak::Label& end) {
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Xbyak::Label nan;
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code.ucomisd(a, b);
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code.jp(nan, code.T_NEAR);
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code.ucomisd(c, c);
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code.jp(nan, code.T_NEAR);
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code.SwitchToFarCode();
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code.L(nan);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.movq(code.ABI_PARAM1, a);
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code.movq(code.ABI_PARAM2, b);
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code.movq(code.ABI_PARAM3, c);
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code.CallFunction(static_cast<u64(*)(u64, u64, u64)>([](u64 a, u64 b, u64 c) -> u64 {
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return *Common::ProcessNaNs(a, b, c);
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}));
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code.movq(a, code.ABI_RETURN);
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(a.getIdx()));
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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}
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static void PostProcessNaNs64(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm tmp) {
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code.movaps(tmp, result);
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code.cmpunordpd(tmp, tmp);
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code.psllq(tmp, 63);
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code.xorps(result, tmp);
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}
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static void DefaultNaN64(BlockOfCode& code, Xbyak::Xmm xmm_value) {
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Xbyak::Label end;
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code.ucomisd(xmm_value, xmm_value);
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code.jnp(end);
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code.movaps(xmm_value, code.MConst(xword, f64_nan));
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code.L(end);
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}
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static Xbyak::Label ProcessNaN32(BlockOfCode& code, Xbyak::Xmm a) {
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Xbyak::Label nan, end;
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code.ucomiss(a, a);
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code.jp(nan, code.T_NEAR);
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code.SwitchToFarCode();
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code.L(nan);
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code.orps(a, code.MConst(xword, 0x00400000));
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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return end;
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}
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static Xbyak::Label ProcessNaN64(BlockOfCode& code, Xbyak::Xmm a) {
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Xbyak::Label nan, end;
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code.ucomisd(a, a);
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code.jp(nan, code.T_NEAR);
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code.SwitchToFarCode();
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code.L(nan);
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code.orps(a, code.MConst(xword, 0x0008'0000'0000'0000));
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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return end;
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}
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template <typename PreprocessFunction, typename Function>
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static void FPThreeOp32(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, [[maybe_unused]] PreprocessFunction preprocess, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Label end;
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Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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Xbyak::Xmm operand = ctx.reg_alloc.UseScratchXmm(args[1]);
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Xbyak::Reg32 gpr_scratch = ctx.reg_alloc.ScratchGpr().cvt32();
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if constexpr(!std::is_same_v<PreprocessFunction, std::nullptr_t>) {
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preprocess(result, operand, gpr_scratch, end);
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}
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if (ctx.FPSCR_FTZ()) {
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DenormalsAreZero32(code, result, gpr_scratch);
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DenormalsAreZero32(code, operand, gpr_scratch);
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}
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if (ctx.AccurateNaN() && !ctx.FPSCR_DN()) {
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PreProcessNaNs32(code, result, operand, end);
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}
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.*fn)(result, operand);
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} else {
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fn(result, operand);
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}
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if (ctx.FPSCR_FTZ()) {
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FlushToZero32(code, result, gpr_scratch);
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}
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if (ctx.FPSCR_DN()) {
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DefaultNaN32(code, result);
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} else if (ctx.AccurateNaN()) {
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PostProcessNaNs32(code, result, operand);
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}
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code.L(end);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename PreprocessFunction, typename Function>
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static void FPThreeOp64(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, [[maybe_unused]] PreprocessFunction preprocess, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Label end;
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Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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Xbyak::Xmm operand = ctx.reg_alloc.UseScratchXmm(args[1]);
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Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
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if constexpr(!std::is_same_v<PreprocessFunction, std::nullptr_t>) {
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preprocess(result, operand, gpr_scratch, end);
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}
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if (ctx.FPSCR_FTZ()) {
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DenormalsAreZero64(code, result, gpr_scratch);
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DenormalsAreZero64(code, operand, gpr_scratch);
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}
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if (ctx.AccurateNaN() && !ctx.FPSCR_DN()) {
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PreProcessNaNs64(code, result, operand, end);
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}
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.*fn)(result, operand);
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} else {
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fn(result, operand);
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}
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if (ctx.FPSCR_FTZ()) {
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FlushToZero64(code, result, gpr_scratch);
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}
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if (ctx.FPSCR_DN()) {
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DefaultNaN64(code, result);
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} else if (ctx.AccurateNaN()) {
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PostProcessNaNs64(code, result, operand);
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}
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code.L(end);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename Function>
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static void FPThreeOp32(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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FPThreeOp32(code, ctx, inst, nullptr, fn);
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}
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template <typename Function>
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static void FPThreeOp64(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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FPThreeOp64(code, ctx, inst, nullptr, fn);
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}
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template <typename Function>
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static void FPTwoOp32(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Label end;
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Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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Xbyak::Reg32 gpr_scratch = ctx.reg_alloc.ScratchGpr().cvt32();
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if (ctx.FPSCR_FTZ()) {
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DenormalsAreZero32(code, result, gpr_scratch);
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}
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if (ctx.AccurateNaN() && !ctx.FPSCR_DN()) {
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end = ProcessNaN32(code, result);
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}
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.*fn)(result, result);
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} else {
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fn(result);
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}
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if (ctx.FPSCR_FTZ()) {
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FlushToZero32(code, result, gpr_scratch);
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}
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if (ctx.FPSCR_DN()) {
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DefaultNaN32(code, result);
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} else if (ctx.AccurateNaN()) {
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PostProcessNaNs32(code, result, ctx.reg_alloc.ScratchXmm());
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}
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code.L(end);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename Function>
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static void FPTwoOp64(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Label end;
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Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
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if (ctx.FPSCR_FTZ()) {
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DenormalsAreZero64(code, result, gpr_scratch);
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}
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if (ctx.AccurateNaN() && !ctx.FPSCR_DN()) {
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end = ProcessNaN64(code, result);
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}
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.*fn)(result, result);
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} else {
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fn(result);
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}
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if (ctx.FPSCR_FTZ()) {
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FlushToZero64(code, result, gpr_scratch);
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}
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if (ctx.FPSCR_DN()) {
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DefaultNaN64(code, result);
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} else if (ctx.AccurateNaN()) {
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PostProcessNaNs64(code, result, ctx.reg_alloc.ScratchXmm());
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}
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code.L(end);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename Function>
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static void FPFourOp32(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Label end;
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Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
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Xbyak::Xmm operand2 = ctx.reg_alloc.UseScratchXmm(args[1]);
|
|
Xbyak::Xmm operand3 = ctx.reg_alloc.UseScratchXmm(args[2]);
|
|
Xbyak::Reg32 gpr_scratch = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero32(code, result, gpr_scratch);
|
|
DenormalsAreZero32(code, operand2, gpr_scratch);
|
|
DenormalsAreZero32(code, operand3, gpr_scratch);
|
|
}
|
|
if (ctx.AccurateNaN() && !ctx.FPSCR_DN()) {
|
|
PreProcessNaNs32(code, result, operand2, operand3, end);
|
|
}
|
|
fn(result, operand2, operand3);
|
|
if (ctx.FPSCR_FTZ()) {
|
|
FlushToZero32(code, result, gpr_scratch);
|
|
}
|
|
if (ctx.FPSCR_DN()) {
|
|
DefaultNaN32(code, result);
|
|
} else if (ctx.AccurateNaN()) {
|
|
PostProcessNaNs32(code, result, operand2);
|
|
}
|
|
code.L(end);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
template <typename Function>
|
|
static void FPFourOp64(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
Xbyak::Label end;
|
|
|
|
Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
Xbyak::Xmm operand2 = ctx.reg_alloc.UseScratchXmm(args[1]);
|
|
Xbyak::Xmm operand3 = ctx.reg_alloc.UseScratchXmm(args[2]);
|
|
Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero64(code, result, gpr_scratch);
|
|
DenormalsAreZero64(code, operand2, gpr_scratch);
|
|
DenormalsAreZero64(code, operand3, gpr_scratch);
|
|
}
|
|
if (ctx.AccurateNaN() && !ctx.FPSCR_DN()) {
|
|
PreProcessNaNs64(code, result, operand2, operand3, end);
|
|
}
|
|
fn(result, operand2, operand3);
|
|
if (ctx.FPSCR_FTZ()) {
|
|
FlushToZero64(code, result, gpr_scratch);
|
|
}
|
|
if (ctx.FPSCR_DN()) {
|
|
DefaultNaN64(code, result);
|
|
} else if (ctx.AccurateNaN()) {
|
|
PostProcessNaNs64(code, result, operand2);
|
|
}
|
|
code.L(end);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
void EmitX64::EmitFPAbs32(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
|
|
code.pand(result, code.MConst(xword, f32_non_sign_mask));
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
void EmitX64::EmitFPAbs64(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
|
|
code.pand(result, code.MConst(xword, f64_non_sign_mask));
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
void EmitX64::EmitFPNeg32(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
|
|
code.pxor(result, code.MConst(xword, f32_negative_zero));
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
void EmitX64::EmitFPNeg64(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
|
|
code.pxor(result, code.MConst(xword, f64_negative_zero));
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
void EmitX64::EmitFPAdd32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, &Xbyak::CodeGenerator::addss);
|
|
}
|
|
|
|
void EmitX64::EmitFPAdd64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, &Xbyak::CodeGenerator::addsd);
|
|
}
|
|
|
|
void EmitX64::EmitFPDiv32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, &Xbyak::CodeGenerator::divss);
|
|
}
|
|
|
|
void EmitX64::EmitFPDiv64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, &Xbyak::CodeGenerator::divsd);
|
|
}
|
|
|
|
void EmitX64::EmitFPMax32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand){
|
|
Xbyak::Label normal, end;
|
|
code.ucomiss(result, operand);
|
|
code.jnz(normal);
|
|
if (!ctx.AccurateNaN()) {
|
|
Xbyak::Label notnan;
|
|
code.jnp(notnan);
|
|
code.addss(result, operand);
|
|
code.jmp(end);
|
|
code.L(notnan);
|
|
}
|
|
code.andps(result, operand);
|
|
code.jmp(end);
|
|
code.L(normal);
|
|
code.maxss(result, operand);
|
|
code.L(end);
|
|
});
|
|
}
|
|
|
|
void EmitX64::EmitFPMax64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand){
|
|
Xbyak::Label normal, end;
|
|
code.ucomisd(result, operand);
|
|
code.jnz(normal);
|
|
if (!ctx.AccurateNaN()) {
|
|
Xbyak::Label notnan;
|
|
code.jnp(notnan);
|
|
code.addsd(result, operand);
|
|
code.jmp(end);
|
|
code.L(notnan);
|
|
}
|
|
code.andps(result, operand);
|
|
code.jmp(end);
|
|
code.L(normal);
|
|
code.maxsd(result, operand);
|
|
code.L(end);
|
|
});
|
|
}
|
|
|
|
void EmitX64::EmitFPMaxNumeric32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand, Xbyak::Reg32 scratch, Xbyak::Label& end){
|
|
Xbyak::Label normal, normal_or_equal, result_is_result;
|
|
|
|
code.ucomiss(result, operand);
|
|
code.jnp(normal_or_equal);
|
|
// If operand == QNaN, result = result.
|
|
code.movd(scratch, operand);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, 0xff800000u);
|
|
code.jae(result_is_result);
|
|
// If operand == SNaN, let usual NaN code handle it.
|
|
code.cmp(scratch, 0xff000000u);
|
|
code.ja(normal);
|
|
// If result == SNaN, && operand != NaN, result = result.
|
|
code.movd(scratch, result);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, 0xff800000u);
|
|
code.jnae(result_is_result);
|
|
// If result == QNaN && operand != NaN, result = operand.
|
|
code.movaps(result, operand);
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.L(result_is_result);
|
|
code.movaps(operand, result);
|
|
code.jmp(normal);
|
|
|
|
code.L(normal_or_equal);
|
|
code.jnz(normal);
|
|
code.andps(operand, result);
|
|
code.L(normal);
|
|
}, &Xbyak::CodeGenerator::maxss);
|
|
}
|
|
|
|
void EmitX64::EmitFPMaxNumeric64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand, Xbyak::Reg64 scratch, Xbyak::Label& end){
|
|
Xbyak::Label normal, normal_or_equal, result_is_result;
|
|
|
|
code.ucomisd(result, operand);
|
|
code.jnp(normal_or_equal);
|
|
// If operand == QNaN, result = result.
|
|
code.movq(scratch, operand);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, code.MConst(qword, 0xfff0'0000'0000'0000u));
|
|
code.jae(result_is_result);
|
|
// If operand == SNaN, let usual NaN code handle it.
|
|
code.cmp(scratch, code.MConst(qword, 0xffe0'0000'0000'0000u));
|
|
code.ja(normal);
|
|
// If result == SNaN, && operand != NaN, result = result.
|
|
code.movq(scratch, result);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, code.MConst(qword, 0xfff0'0000'0000'0000u));
|
|
code.jnae(result_is_result);
|
|
// If result == QNaN && operand != NaN, result = operand.
|
|
code.movaps(result, operand);
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.L(result_is_result);
|
|
code.movaps(operand, result);
|
|
code.jmp(normal);
|
|
|
|
code.L(normal_or_equal);
|
|
code.jnz(normal);
|
|
code.andps(operand, result);
|
|
code.L(normal);
|
|
}, &Xbyak::CodeGenerator::maxsd);
|
|
}
|
|
|
|
void EmitX64::EmitFPMin32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand){
|
|
Xbyak::Label normal, end;
|
|
code.ucomiss(result, operand);
|
|
code.jnz(normal);
|
|
code.orps(result, operand);
|
|
code.jmp(end);
|
|
code.L(normal);
|
|
code.minss(result, operand);
|
|
code.L(end);
|
|
});
|
|
}
|
|
|
|
void EmitX64::EmitFPMin64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand){
|
|
Xbyak::Label normal, end;
|
|
code.ucomisd(result, operand);
|
|
code.jnz(normal);
|
|
code.orps(result, operand);
|
|
code.jmp(end);
|
|
code.L(normal);
|
|
code.minsd(result, operand);
|
|
code.L(end);
|
|
});
|
|
}
|
|
|
|
|
|
void EmitX64::EmitFPMinNumeric32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand, Xbyak::Reg32 scratch, Xbyak::Label& end){
|
|
Xbyak::Label normal, normal_or_equal, result_is_result;
|
|
|
|
code.ucomiss(result, operand);
|
|
code.jnp(normal_or_equal);
|
|
// If operand == QNaN, result = result.
|
|
code.movd(scratch, operand);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, 0xff800000u);
|
|
code.jae(result_is_result);
|
|
// If operand == SNaN, let usual NaN code handle it.
|
|
code.cmp(scratch, 0xff000000u);
|
|
code.ja(normal);
|
|
// If result == SNaN, && operand != NaN, result = result.
|
|
code.movd(scratch, result);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, 0xff800000u);
|
|
code.jnae(result_is_result);
|
|
// If result == QNaN && operand != NaN, result = operand.
|
|
code.movaps(result, operand);
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.L(result_is_result);
|
|
code.movaps(operand, result);
|
|
code.jmp(normal);
|
|
|
|
code.L(normal_or_equal);
|
|
code.jnz(normal);
|
|
code.orps(operand, result);
|
|
code.L(normal);
|
|
}, &Xbyak::CodeGenerator::minss);
|
|
}
|
|
|
|
void EmitX64::EmitFPMinNumeric64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand, Xbyak::Reg64 scratch, Xbyak::Label& end){
|
|
Xbyak::Label normal, normal_or_equal, result_is_result;
|
|
|
|
code.ucomisd(result, operand);
|
|
code.jnp(normal_or_equal);
|
|
// If operand == QNaN, result = result.
|
|
code.movq(scratch, operand);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, code.MConst(qword, 0xfff0'0000'0000'0000u));
|
|
code.jae(result_is_result);
|
|
// If operand == SNaN, let usual NaN code handle it.
|
|
code.cmp(scratch, code.MConst(qword, 0xffe0'0000'0000'0000u));
|
|
code.ja(normal);
|
|
// If result == SNaN, && operand != NaN, result = result.
|
|
code.movq(scratch, result);
|
|
code.shl(scratch, 1);
|
|
code.cmp(scratch, code.MConst(qword, 0xfff0'0000'0000'0000u));
|
|
code.jnae(result_is_result);
|
|
// If result == QNaN && operand != NaN, result = operand.
|
|
code.movaps(result, operand);
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.L(result_is_result);
|
|
code.movaps(operand, result);
|
|
code.jmp(normal);
|
|
|
|
code.L(normal_or_equal);
|
|
code.jnz(normal);
|
|
code.orps(operand, result);
|
|
code.L(normal);
|
|
}, &Xbyak::CodeGenerator::minsd);
|
|
}
|
|
|
|
void EmitX64::EmitFPMul32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, &Xbyak::CodeGenerator::mulss);
|
|
}
|
|
|
|
void EmitX64::EmitFPMul64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, &Xbyak::CodeGenerator::mulsd);
|
|
}
|
|
|
|
void EmitX64::EmitFPMulAdd32(EmitContext& ctx, IR::Inst* inst) {
|
|
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
|
|
FPFourOp32(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand2, Xbyak::Xmm operand3) {
|
|
code.vfmadd231ss(result, operand2, operand3);
|
|
});
|
|
return;
|
|
}
|
|
|
|
// TODO: Improve accuracy.
|
|
FPFourOp32(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand2, Xbyak::Xmm operand3) {
|
|
code.mulss(operand2, operand3);
|
|
code.addss(result, operand2);
|
|
});
|
|
}
|
|
|
|
void EmitX64::EmitFPMulAdd64(EmitContext& ctx, IR::Inst* inst) {
|
|
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
|
|
FPFourOp64(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand2, Xbyak::Xmm operand3) {
|
|
code.vfmadd231sd(result, operand2, operand3);
|
|
});
|
|
return;
|
|
}
|
|
|
|
// TODO: Improve accuracy.
|
|
FPFourOp64(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand2, Xbyak::Xmm operand3) {
|
|
code.mulsd(operand2, operand3);
|
|
code.addsd(result, operand2);
|
|
});
|
|
}
|
|
|
|
void EmitX64::EmitFPSqrt32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPTwoOp32(code, ctx, inst, &Xbyak::CodeGenerator::sqrtss);
|
|
}
|
|
|
|
void EmitX64::EmitFPSqrt64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPTwoOp64(code, ctx, inst, &Xbyak::CodeGenerator::sqrtsd);
|
|
}
|
|
|
|
void EmitX64::EmitFPSub32(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp32(code, ctx, inst, &Xbyak::CodeGenerator::subss);
|
|
}
|
|
|
|
void EmitX64::EmitFPSub64(EmitContext& ctx, IR::Inst* inst) {
|
|
FPThreeOp64(code, ctx, inst, &Xbyak::CodeGenerator::subsd);
|
|
}
|
|
|
|
static Xbyak::Reg64 SetFpscrNzcvFromFlags(BlockOfCode& code, EmitContext& ctx) {
|
|
ctx.reg_alloc.ScratchGpr({HostLoc::RCX}); // shifting requires use of cl
|
|
Xbyak::Reg64 nzcv = ctx.reg_alloc.ScratchGpr();
|
|
|
|
// x64 flags ARM flags
|
|
// ZF PF CF NZCV
|
|
// Unordered 1 1 1 0011
|
|
// Greater than 0 0 0 0010
|
|
// Less than 0 0 1 1000
|
|
// Equal 1 0 0 0110
|
|
//
|
|
// Thus we can take use ZF:CF as an index into an array like so:
|
|
// x64 ARM ARM as x64
|
|
// ZF:CF NZCV NZ-----C-------V
|
|
// 0 0010 0000000100000000 = 0x0100
|
|
// 1 1000 1000000000000000 = 0x8000
|
|
// 2 0110 0100000100000000 = 0x4100
|
|
// 3 0011 0000000100000001 = 0x0101
|
|
|
|
code.mov(nzcv, 0x0101'4100'8000'0100);
|
|
code.sete(cl);
|
|
code.rcl(cl, 5); // cl = ZF:CF:0000
|
|
code.shr(nzcv, cl);
|
|
|
|
return nzcv;
|
|
}
|
|
|
|
void EmitX64::EmitFPCompare32(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm reg_a = ctx.reg_alloc.UseXmm(args[0]);
|
|
Xbyak::Xmm reg_b = ctx.reg_alloc.UseXmm(args[1]);
|
|
bool exc_on_qnan = args[2].GetImmediateU1();
|
|
|
|
if (exc_on_qnan) {
|
|
code.comiss(reg_a, reg_b);
|
|
} else {
|
|
code.ucomiss(reg_a, reg_b);
|
|
}
|
|
|
|
Xbyak::Reg64 nzcv = SetFpscrNzcvFromFlags(code, ctx);
|
|
ctx.reg_alloc.DefineValue(inst, nzcv);
|
|
}
|
|
|
|
void EmitX64::EmitFPCompare64(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm reg_a = ctx.reg_alloc.UseXmm(args[0]);
|
|
Xbyak::Xmm reg_b = ctx.reg_alloc.UseXmm(args[1]);
|
|
bool exc_on_qnan = args[2].GetImmediateU1();
|
|
|
|
if (exc_on_qnan) {
|
|
code.comisd(reg_a, reg_b);
|
|
} else {
|
|
code.ucomisd(reg_a, reg_b);
|
|
}
|
|
|
|
Xbyak::Reg64 nzcv = SetFpscrNzcvFromFlags(code, ctx);
|
|
ctx.reg_alloc.DefineValue(inst, nzcv);
|
|
}
|
|
|
|
void EmitX64::EmitFPSingleToDouble(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero32(code, result, gpr_scratch.cvt32());
|
|
}
|
|
code.cvtss2sd(result, result);
|
|
if (ctx.FPSCR_FTZ()) {
|
|
FlushToZero64(code, result, gpr_scratch);
|
|
}
|
|
if (ctx.FPSCR_DN()) {
|
|
DefaultNaN64(code, result);
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
void EmitX64::EmitFPDoubleToSingle(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero64(code, result, gpr_scratch);
|
|
}
|
|
code.cvtsd2ss(result, result);
|
|
if (ctx.FPSCR_FTZ()) {
|
|
FlushToZero32(code, result, gpr_scratch.cvt32());
|
|
}
|
|
if (ctx.FPSCR_DN()) {
|
|
DefaultNaN32(code, result);
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
}
|
|
|
|
void EmitX64::EmitFPSingleToS32(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm from = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
Xbyak::Reg32 to = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
Xbyak::Xmm xmm_scratch = ctx.reg_alloc.ScratchXmm();
|
|
bool round_towards_zero = args[1].GetImmediateU1();
|
|
|
|
// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
|
|
// Conversion to double is lossless, and allows for clamping.
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero32(code, from, to);
|
|
}
|
|
code.cvtss2sd(from, from);
|
|
// First time is to set flags
|
|
if (round_towards_zero) {
|
|
code.cvttsd2si(to, from); // 32 bit gpr
|
|
} else {
|
|
code.cvtsd2si(to, from); // 32 bit gpr
|
|
}
|
|
// Clamp to output range
|
|
ZeroIfNaN64(code, from, xmm_scratch);
|
|
code.minsd(from, code.MConst(xword, f64_max_s32));
|
|
code.maxsd(from, code.MConst(xword, f64_min_s32));
|
|
// Second time is for real
|
|
if (round_towards_zero) {
|
|
code.cvttsd2si(to, from); // 32 bit gpr
|
|
} else {
|
|
code.cvtsd2si(to, from); // 32 bit gpr
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
void EmitX64::EmitFPSingleToU32(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm from = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
Xbyak::Reg64 to = ctx.reg_alloc.ScratchGpr().cvt64();
|
|
Xbyak::Xmm xmm_scratch = ctx.reg_alloc.ScratchXmm();
|
|
bool round_towards_zero = args[1].GetImmediateU1();
|
|
|
|
// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
|
|
// Conversion to double is lossless, and allows for accurate clamping.
|
|
//
|
|
// Since SSE2 doesn't provide an unsigned conversion, we use a 64-bit signed conversion.
|
|
//
|
|
// FIXME: None of the FPSR exception bits are correctly signalled with the below code
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero64(code, from, to);
|
|
}
|
|
code.cvtss2sd(from, from);
|
|
// Clamp to output range
|
|
ZeroIfNaN64(code, from, xmm_scratch);
|
|
code.minsd(from, code.MConst(xword, f64_max_u32));
|
|
code.maxsd(from, code.MConst(xword, f64_min_u32));
|
|
if (round_towards_zero) {
|
|
code.cvttsd2si(to, from); // 64 bit gpr
|
|
} else {
|
|
code.cvtsd2si(to, from); // 64 bit gpr
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
void EmitX64::EmitFPDoubleToS32(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm from = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
Xbyak::Reg32 to = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
Xbyak::Xmm xmm_scratch = ctx.reg_alloc.ScratchXmm();
|
|
Xbyak::Reg32 gpr_scratch = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
bool round_towards_zero = args[1].GetImmediateU1();
|
|
|
|
// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero64(code, from, gpr_scratch.cvt64());
|
|
}
|
|
// First time is to set flags
|
|
if (round_towards_zero) {
|
|
code.cvttsd2si(gpr_scratch, from); // 32 bit gpr
|
|
} else {
|
|
code.cvtsd2si(gpr_scratch, from); // 32 bit gpr
|
|
}
|
|
// Clamp to output range
|
|
ZeroIfNaN64(code, from, xmm_scratch);
|
|
code.minsd(from, code.MConst(xword, f64_max_s32));
|
|
code.maxsd(from, code.MConst(xword, f64_min_s32));
|
|
// Second time is for real
|
|
if (round_towards_zero) {
|
|
code.cvttsd2si(to, from); // 32 bit gpr
|
|
} else {
|
|
code.cvtsd2si(to, from); // 32 bit gpr
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
void EmitX64::EmitFPDoubleToU32(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Xmm from = ctx.reg_alloc.UseScratchXmm(args[0]);
|
|
Xbyak::Reg64 to = ctx.reg_alloc.ScratchGpr().cvt64();
|
|
Xbyak::Xmm xmm_scratch = ctx.reg_alloc.ScratchXmm();
|
|
bool round_towards_zero = args[1].GetImmediateU1();
|
|
|
|
// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
|
|
// TODO: Use VCVTPD2UDQ when AVX512VL is available.
|
|
// FIXME: None of the FPSR exception bits are correctly signalled with the below code
|
|
|
|
if (ctx.FPSCR_FTZ()) {
|
|
DenormalsAreZero64(code, from, to);
|
|
}
|
|
// Clamp to output range
|
|
ZeroIfNaN64(code, from, xmm_scratch);
|
|
code.minsd(from, code.MConst(xword, f64_max_u32));
|
|
code.maxsd(from, code.MConst(xword, f64_min_u32));
|
|
if (round_towards_zero) {
|
|
code.cvttsd2si(to, from); // 64 bit gpr
|
|
} else {
|
|
code.cvtsd2si(to, from); // 64 bit gpr
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
void EmitX64::EmitFPS32ToSingle(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Reg32 from = ctx.reg_alloc.UseGpr(args[0]).cvt32();
|
|
Xbyak::Xmm to = ctx.reg_alloc.ScratchXmm();
|
|
bool round_to_nearest = args[1].GetImmediateU1();
|
|
ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
|
|
|
|
code.cvtsi2ss(to, from);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
void EmitX64::EmitFPU32ToSingle(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
|
|
Xbyak::Xmm to = ctx.reg_alloc.ScratchXmm();
|
|
bool round_to_nearest = args[1].GetImmediateU1();
|
|
ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
|
|
|
|
// We are using a 64-bit GPR register to ensure we don't end up treating the input as signed
|
|
code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary
|
|
code.cvtsi2ss(to, from);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
void EmitX64::EmitFPS32ToDouble(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Reg32 from = ctx.reg_alloc.UseGpr(args[0]).cvt32();
|
|
Xbyak::Xmm to = ctx.reg_alloc.ScratchXmm();
|
|
bool round_to_nearest = args[1].GetImmediateU1();
|
|
ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
|
|
|
|
code.cvtsi2sd(to, from);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
void EmitX64::EmitFPU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
|
|
Xbyak::Xmm to = ctx.reg_alloc.ScratchXmm();
|
|
bool round_to_nearest = args[1].GetImmediateU1();
|
|
ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
|
|
|
|
// We are using a 64-bit GPR register to ensure we don't end up treating the input as signed
|
|
code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary
|
|
code.cvtsi2sd(to, from);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, to);
|
|
}
|
|
|
|
} // namespace Dynarmic::BackendX64
|