653 lines
20 KiB
C++
653 lines
20 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include <fmt/ostream.h>
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#include "common/assert.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/opcodes.h"
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#include "frontend/ir/type.h"
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namespace Dynarmic::IR {
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bool Inst::IsArithmeticShift() const {
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return op == Opcode::ArithmeticShiftRight32 ||
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op == Opcode::ArithmeticShiftRight64;
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}
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bool Inst::IsCircularShift() const {
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return op == Opcode::RotateRight32 ||
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op == Opcode::RotateRight64 ||
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op == Opcode::RotateRightExtended;
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}
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bool Inst::IsLogicalShift() const {
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switch (op) {
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case Opcode::LogicalShiftLeft32:
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case Opcode::LogicalShiftLeft64:
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case Opcode::LogicalShiftRight32:
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case Opcode::LogicalShiftRight64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsShift() const {
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return IsArithmeticShift() ||
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IsCircularShift() ||
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IsLogicalShift();
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}
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bool Inst::IsSharedMemoryRead() const {
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switch (op) {
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case Opcode::A32ReadMemory8:
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case Opcode::A32ReadMemory16:
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case Opcode::A32ReadMemory32:
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case Opcode::A32ReadMemory64:
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case Opcode::A64ReadMemory8:
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case Opcode::A64ReadMemory16:
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case Opcode::A64ReadMemory32:
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case Opcode::A64ReadMemory64:
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case Opcode::A64ReadMemory128:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsSharedMemoryWrite() const {
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switch (op) {
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case Opcode::A32WriteMemory8:
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case Opcode::A32WriteMemory16:
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case Opcode::A32WriteMemory32:
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case Opcode::A32WriteMemory64:
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case Opcode::A64WriteMemory8:
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case Opcode::A64WriteMemory16:
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case Opcode::A64WriteMemory32:
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case Opcode::A64WriteMemory64:
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case Opcode::A64WriteMemory128:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsSharedMemoryReadOrWrite() const {
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return IsSharedMemoryRead() || IsSharedMemoryWrite();
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}
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bool Inst::IsExclusiveMemoryWrite() const {
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switch (op) {
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case Opcode::A32ExclusiveWriteMemory8:
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case Opcode::A32ExclusiveWriteMemory16:
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case Opcode::A32ExclusiveWriteMemory32:
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case Opcode::A32ExclusiveWriteMemory64:
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case Opcode::A64ExclusiveWriteMemory8:
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case Opcode::A64ExclusiveWriteMemory16:
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case Opcode::A64ExclusiveWriteMemory32:
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case Opcode::A64ExclusiveWriteMemory64:
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case Opcode::A64ExclusiveWriteMemory128:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsMemoryRead() const {
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return IsSharedMemoryRead();
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}
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bool Inst::IsMemoryWrite() const {
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return IsSharedMemoryWrite() || IsExclusiveMemoryWrite();
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}
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bool Inst::IsMemoryReadOrWrite() const {
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return IsMemoryRead() || IsMemoryWrite();
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}
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bool Inst::ReadsFromCPSR() const {
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switch (op) {
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case Opcode::A32GetCpsr:
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case Opcode::A32GetNFlag:
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case Opcode::A32GetZFlag:
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case Opcode::A32GetCFlag:
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case Opcode::A32GetVFlag:
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case Opcode::A32GetGEFlags:
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case Opcode::A64GetCFlag:
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case Opcode::A64GetNZCVRaw:
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case Opcode::ConditionalSelect32:
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case Opcode::ConditionalSelect64:
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case Opcode::ConditionalSelectNZCV:
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return true;
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default:
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return false;
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}
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}
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bool Inst::WritesToCPSR() const {
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switch (op) {
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case Opcode::A32SetCpsr:
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case Opcode::A32SetCpsrNZCV:
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case Opcode::A32SetCpsrNZCVQ:
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case Opcode::A32SetNFlag:
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case Opcode::A32SetZFlag:
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case Opcode::A32SetCFlag:
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case Opcode::A32SetVFlag:
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case Opcode::A32OrQFlag:
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case Opcode::A32SetGEFlags:
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case Opcode::A32SetGEFlagsCompressed:
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case Opcode::A64SetNZCVRaw:
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case Opcode::A64SetNZCV:
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return true;
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default:
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return false;
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}
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}
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bool Inst::WritesToSystemRegister() const {
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switch (op) {
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case Opcode::A64SetTPIDR:
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return true;
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default:
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return false;
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}
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}
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bool Inst::ReadsFromCoreRegister() const {
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switch (op) {
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case Opcode::A32GetRegister:
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case Opcode::A32GetExtendedRegister32:
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case Opcode::A32GetExtendedRegister64:
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case Opcode::A64GetW:
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case Opcode::A64GetX:
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case Opcode::A64GetS:
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case Opcode::A64GetD:
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case Opcode::A64GetQ:
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case Opcode::A64GetSP:
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return true;
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default:
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return false;
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}
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}
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bool Inst::WritesToCoreRegister() const {
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switch (op) {
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case Opcode::A32SetRegister:
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case Opcode::A32SetExtendedRegister32:
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case Opcode::A32SetExtendedRegister64:
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case Opcode::A32BXWritePC:
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case Opcode::A64SetW:
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case Opcode::A64SetX:
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case Opcode::A64SetS:
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case Opcode::A64SetD:
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case Opcode::A64SetQ:
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case Opcode::A64SetSP:
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case Opcode::A64SetPC:
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return true;
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default:
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return false;
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}
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}
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bool Inst::ReadsFromFPCR() const {
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switch (op) {
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case Opcode::A32GetFpscr:
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case Opcode::A32GetFpscrNZCV:
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case Opcode::A64GetFPCR:
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return true;
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default:
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return false;
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}
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}
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bool Inst::WritesToFPCR() const {
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switch (op) {
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case Opcode::A32SetFpscr:
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case Opcode::A32SetFpscrNZCV:
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case Opcode::A64SetFPCR:
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return true;
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default:
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return false;
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}
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}
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bool Inst::ReadsFromFPSR() const {
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return op == Opcode::A32GetFpscr ||
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op == Opcode::A32GetFpscrNZCV ||
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op == Opcode::A64GetFPSR ||
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ReadsFromFPSRCumulativeExceptionBits() ||
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ReadsFromFPSRCumulativeSaturationBit();
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}
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bool Inst::WritesToFPSR() const {
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return op == Opcode::A32SetFpscr ||
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op == Opcode::A32SetFpscrNZCV ||
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op == Opcode::A64SetFPSR ||
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WritesToFPSRCumulativeExceptionBits() ||
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WritesToFPSRCumulativeSaturationBit();
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}
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bool Inst::ReadsFromFPSRCumulativeExceptionBits() const {
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return ReadsFromAndWritesToFPSRCumulativeExceptionBits();
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}
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bool Inst::WritesToFPSRCumulativeExceptionBits() const {
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return ReadsFromAndWritesToFPSRCumulativeExceptionBits();
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}
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bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
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switch (op) {
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case Opcode::FPAdd32:
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case Opcode::FPAdd64:
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case Opcode::FPCompare32:
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case Opcode::FPCompare64:
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case Opcode::FPDiv32:
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case Opcode::FPDiv64:
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case Opcode::FPMax32:
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case Opcode::FPMax64:
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case Opcode::FPMaxNumeric32:
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case Opcode::FPMaxNumeric64:
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case Opcode::FPMin32:
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case Opcode::FPMin64:
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case Opcode::FPMinNumeric32:
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case Opcode::FPMinNumeric64:
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case Opcode::FPMul32:
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case Opcode::FPMul64:
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case Opcode::FPMulAdd16:
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case Opcode::FPMulAdd32:
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case Opcode::FPMulAdd64:
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case Opcode::FPRecipEstimate32:
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case Opcode::FPRecipEstimate64:
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case Opcode::FPRecipExponent16:
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case Opcode::FPRecipExponent32:
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case Opcode::FPRecipExponent64:
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case Opcode::FPRecipStepFused32:
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case Opcode::FPRecipStepFused64:
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case Opcode::FPRoundInt32:
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case Opcode::FPRoundInt64:
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case Opcode::FPRSqrtEstimate32:
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case Opcode::FPRSqrtEstimate64:
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case Opcode::FPRSqrtStepFused32:
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case Opcode::FPRSqrtStepFused64:
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case Opcode::FPSqrt32:
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case Opcode::FPSqrt64:
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case Opcode::FPSub32:
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case Opcode::FPSub64:
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case Opcode::FPHalfToDouble:
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case Opcode::FPHalfToSingle:
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case Opcode::FPSingleToDouble:
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case Opcode::FPSingleToHalf:
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case Opcode::FPDoubleToHalf:
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case Opcode::FPDoubleToSingle:
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case Opcode::FPDoubleToFixedS32:
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case Opcode::FPDoubleToFixedS64:
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case Opcode::FPDoubleToFixedU32:
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case Opcode::FPDoubleToFixedU64:
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case Opcode::FPSingleToFixedS32:
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case Opcode::FPSingleToFixedS64:
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case Opcode::FPSingleToFixedU32:
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case Opcode::FPSingleToFixedU64:
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case Opcode::FPFixedU32ToSingle:
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case Opcode::FPFixedS32ToSingle:
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case Opcode::FPFixedU32ToDouble:
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case Opcode::FPFixedU64ToDouble:
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case Opcode::FPFixedU64ToSingle:
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case Opcode::FPFixedS32ToDouble:
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case Opcode::FPFixedS64ToDouble:
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case Opcode::FPFixedS64ToSingle:
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case Opcode::FPVectorAdd32:
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case Opcode::FPVectorAdd64:
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case Opcode::FPVectorDiv32:
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case Opcode::FPVectorDiv64:
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case Opcode::FPVectorEqual32:
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case Opcode::FPVectorEqual64:
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case Opcode::FPVectorFromSignedFixed32:
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case Opcode::FPVectorFromSignedFixed64:
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case Opcode::FPVectorFromUnsignedFixed32:
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case Opcode::FPVectorFromUnsignedFixed64:
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case Opcode::FPVectorGreater32:
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case Opcode::FPVectorGreater64:
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case Opcode::FPVectorGreaterEqual32:
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case Opcode::FPVectorGreaterEqual64:
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case Opcode::FPVectorMul32:
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case Opcode::FPVectorMul64:
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case Opcode::FPVectorMulAdd32:
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case Opcode::FPVectorMulAdd64:
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case Opcode::FPVectorPairedAddLower32:
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case Opcode::FPVectorPairedAddLower64:
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case Opcode::FPVectorPairedAdd32:
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case Opcode::FPVectorPairedAdd64:
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case Opcode::FPVectorRecipEstimate32:
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case Opcode::FPVectorRecipEstimate64:
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case Opcode::FPVectorRecipStepFused32:
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case Opcode::FPVectorRecipStepFused64:
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case Opcode::FPVectorRSqrtEstimate32:
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case Opcode::FPVectorRSqrtEstimate64:
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case Opcode::FPVectorRSqrtStepFused32:
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case Opcode::FPVectorRSqrtStepFused64:
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case Opcode::FPVectorSqrt32:
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case Opcode::FPVectorSqrt64:
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case Opcode::FPVectorSub32:
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case Opcode::FPVectorSub64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::ReadsFromFPSRCumulativeSaturationBit() const {
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return false;
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}
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bool Inst::WritesToFPSRCumulativeSaturationBit() const {
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switch (op) {
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case Opcode::A64OrQC:
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case Opcode::VectorSignedSaturatedAbs8:
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case Opcode::VectorSignedSaturatedAbs16:
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case Opcode::VectorSignedSaturatedAbs32:
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case Opcode::VectorSignedSaturatedAbs64:
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case Opcode::VectorSignedSaturatedAccumulateUnsigned8:
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case Opcode::VectorSignedSaturatedAccumulateUnsigned16:
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case Opcode::VectorSignedSaturatedAccumulateUnsigned32:
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case Opcode::VectorSignedSaturatedAccumulateUnsigned64:
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case Opcode::VectorSignedSaturatedDoublingMultiply16:
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case Opcode::VectorSignedSaturatedDoublingMultiply32:
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case Opcode::VectorSignedSaturatedDoublingMultiplyLong16:
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case Opcode::VectorSignedSaturatedDoublingMultiplyLong32:
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case Opcode::VectorSignedSaturatedNarrowToSigned16:
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case Opcode::VectorSignedSaturatedNarrowToSigned32:
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case Opcode::VectorSignedSaturatedNarrowToSigned64:
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case Opcode::VectorSignedSaturatedNarrowToUnsigned16:
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case Opcode::VectorSignedSaturatedNarrowToUnsigned32:
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case Opcode::VectorSignedSaturatedNarrowToUnsigned64:
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case Opcode::VectorSignedSaturatedNeg8:
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case Opcode::VectorSignedSaturatedNeg16:
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case Opcode::VectorSignedSaturatedNeg32:
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case Opcode::VectorSignedSaturatedNeg64:
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case Opcode::VectorSignedSaturatedShiftLeft8:
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case Opcode::VectorSignedSaturatedShiftLeft16:
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case Opcode::VectorSignedSaturatedShiftLeft32:
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case Opcode::VectorSignedSaturatedShiftLeft64:
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case Opcode::VectorUnsignedSaturatedAccumulateSigned8:
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case Opcode::VectorUnsignedSaturatedAccumulateSigned16:
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case Opcode::VectorUnsignedSaturatedAccumulateSigned32:
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case Opcode::VectorUnsignedSaturatedAccumulateSigned64:
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case Opcode::VectorUnsignedSaturatedNarrow16:
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case Opcode::VectorUnsignedSaturatedNarrow32:
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case Opcode::VectorUnsignedSaturatedNarrow64:
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case Opcode::VectorUnsignedSaturatedShiftLeft8:
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case Opcode::VectorUnsignedSaturatedShiftLeft16:
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case Opcode::VectorUnsignedSaturatedShiftLeft32:
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case Opcode::VectorUnsignedSaturatedShiftLeft64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::CausesCPUException() const {
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return op == Opcode::Breakpoint ||
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op == Opcode::A32CallSupervisor ||
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op == Opcode::A32ExceptionRaised ||
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op == Opcode::A64CallSupervisor ||
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op == Opcode::A64ExceptionRaised;
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}
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bool Inst::AltersExclusiveState() const {
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return op == Opcode::A32ClearExclusive ||
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op == Opcode::A32SetExclusive ||
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op == Opcode::A64ClearExclusive ||
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op == Opcode::A64SetExclusive ||
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IsExclusiveMemoryWrite();
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}
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bool Inst::IsCoprocessorInstruction() const {
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switch (op) {
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case Opcode::A32CoprocInternalOperation:
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case Opcode::A32CoprocSendOneWord:
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case Opcode::A32CoprocSendTwoWords:
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case Opcode::A32CoprocGetOneWord:
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case Opcode::A32CoprocGetTwoWords:
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case Opcode::A32CoprocLoadWords:
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case Opcode::A32CoprocStoreWords:
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return true;
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default:
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return false;
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}
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}
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bool Inst::MayHaveSideEffects() const {
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return op == Opcode::PushRSB ||
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op == Opcode::A64SetCheckBit ||
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op == Opcode::A64DataCacheOperationRaised ||
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op == Opcode::A64DataSynchronizationBarrier ||
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op == Opcode::A64DataMemoryBarrier ||
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op == Opcode::A64InstructionSynchronizationBarrier ||
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CausesCPUException() ||
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WritesToCoreRegister() ||
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WritesToSystemRegister() ||
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WritesToCPSR() ||
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WritesToFPCR() ||
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WritesToFPSR() ||
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AltersExclusiveState() ||
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IsMemoryWrite() ||
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IsCoprocessorInstruction();
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}
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bool Inst::IsAPseudoOperation() const {
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switch (op) {
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case Opcode::GetCarryFromOp:
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case Opcode::GetOverflowFromOp:
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case Opcode::GetGEFromOp:
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case Opcode::GetNZCVFromOp:
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case Opcode::GetUpperFromOp:
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case Opcode::GetLowerFromOp:
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return true;
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default:
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return false;
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}
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}
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bool Inst::MayGetNZCVFromOp() const {
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switch (op) {
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case Opcode::Add32:
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case Opcode::Add64:
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case Opcode::Sub32:
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case Opcode::Sub64:
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case Opcode::And32:
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case Opcode::And64:
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case Opcode::Eor32:
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case Opcode::Eor64:
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case Opcode::Or32:
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case Opcode::Or64:
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case Opcode::Not32:
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case Opcode::Not64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::AreAllArgsImmediates() const {
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return std::all_of(args.begin(), args.begin() + NumArgs(), [](const auto& value){ return value.IsImmediate(); });
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}
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bool Inst::HasAssociatedPseudoOperation() const {
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return carry_inst || overflow_inst || ge_inst || nzcv_inst || upper_inst || lower_inst;
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}
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Inst* Inst::GetAssociatedPseudoOperation(Opcode opcode) {
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// This is faster than doing a search through the block.
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switch (opcode) {
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case Opcode::GetCarryFromOp:
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ASSERT(!carry_inst || carry_inst->GetOpcode() == Opcode::GetCarryFromOp);
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return carry_inst;
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case Opcode::GetOverflowFromOp:
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ASSERT(!overflow_inst || overflow_inst->GetOpcode() == Opcode::GetOverflowFromOp);
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return overflow_inst;
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case Opcode::GetGEFromOp:
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ASSERT(!ge_inst || ge_inst->GetOpcode() == Opcode::GetGEFromOp);
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return ge_inst;
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case Opcode::GetNZCVFromOp:
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ASSERT(!nzcv_inst || nzcv_inst->GetOpcode() == Opcode::GetNZCVFromOp);
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return nzcv_inst;
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case Opcode::GetUpperFromOp:
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ASSERT(!upper_inst || upper_inst->GetOpcode() == Opcode::GetUpperFromOp);
|
|
return upper_inst;
|
|
case Opcode::GetLowerFromOp:
|
|
ASSERT(!lower_inst || lower_inst->GetOpcode() == Opcode::GetLowerFromOp);
|
|
return lower_inst;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
ASSERT_MSG(false, "Not a valid pseudo-operation");
|
|
return nullptr;
|
|
}
|
|
|
|
Type Inst::GetType() const {
|
|
if (op == Opcode::Identity)
|
|
return args[0].GetType();
|
|
return GetTypeOf(op);
|
|
}
|
|
|
|
size_t Inst::NumArgs() const {
|
|
return GetNumArgsOf(op);
|
|
}
|
|
|
|
Value Inst::GetArg(size_t index) const {
|
|
ASSERT_MSG(index < GetNumArgsOf(op), "Inst::GetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
|
|
ASSERT_MSG(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque, "Inst::GetArg: index {} is empty", index, args[index].GetType());
|
|
|
|
return args[index];
|
|
}
|
|
|
|
void Inst::SetArg(size_t index, Value value) {
|
|
ASSERT_MSG(index < GetNumArgsOf(op), "Inst::SetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
|
|
ASSERT_MSG(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)), "Inst::SetArg: type {} of argument {} not compatible with operation {} ({})", value.GetType(), index, op, GetArgTypeOf(op, index));
|
|
|
|
if (!args[index].IsImmediate()) {
|
|
UndoUse(args[index]);
|
|
}
|
|
if (!value.IsImmediate()) {
|
|
Use(value);
|
|
}
|
|
|
|
args[index] = value;
|
|
}
|
|
|
|
void Inst::Invalidate() {
|
|
ClearArgs();
|
|
op = Opcode::Void;
|
|
}
|
|
|
|
void Inst::ClearArgs() {
|
|
for (auto& value : args) {
|
|
if (!value.IsImmediate()) {
|
|
UndoUse(value);
|
|
}
|
|
value = {};
|
|
}
|
|
}
|
|
|
|
void Inst::ReplaceUsesWith(Value replacement) {
|
|
Invalidate();
|
|
|
|
op = Opcode::Identity;
|
|
|
|
if (!replacement.IsImmediate()) {
|
|
Use(replacement);
|
|
}
|
|
|
|
args[0] = replacement;
|
|
}
|
|
|
|
void Inst::Use(const Value& value) {
|
|
value.GetInst()->use_count++;
|
|
|
|
switch (op){
|
|
case Opcode::GetCarryFromOp:
|
|
ASSERT_MSG(!value.GetInst()->carry_inst, "Only one of each type of pseudo-op allowed");
|
|
value.GetInst()->carry_inst = this;
|
|
break;
|
|
case Opcode::GetOverflowFromOp:
|
|
ASSERT_MSG(!value.GetInst()->overflow_inst, "Only one of each type of pseudo-op allowed");
|
|
value.GetInst()->overflow_inst = this;
|
|
break;
|
|
case Opcode::GetGEFromOp:
|
|
ASSERT_MSG(!value.GetInst()->ge_inst, "Only one of each type of pseudo-op allowed");
|
|
value.GetInst()->ge_inst = this;
|
|
break;
|
|
case Opcode::GetNZCVFromOp:
|
|
ASSERT_MSG(!value.GetInst()->nzcv_inst, "Only one of each type of pseudo-op allowed");
|
|
ASSERT_MSG(value.GetInst()->MayGetNZCVFromOp(), "This value doesn't support the GetNZCVFromOp pseduo-op");
|
|
value.GetInst()->nzcv_inst = this;
|
|
break;
|
|
case Opcode::GetUpperFromOp:
|
|
ASSERT_MSG(!value.GetInst()->upper_inst, "Only one of each type of pseudo-op allowed");
|
|
value.GetInst()->upper_inst = this;
|
|
break;
|
|
case Opcode::GetLowerFromOp:
|
|
ASSERT_MSG(!value.GetInst()->lower_inst, "Only one of each type of pseudo-op allowed");
|
|
value.GetInst()->lower_inst = this;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Inst::UndoUse(const Value& value) {
|
|
value.GetInst()->use_count--;
|
|
|
|
switch (op){
|
|
case Opcode::GetCarryFromOp:
|
|
ASSERT(value.GetInst()->carry_inst->GetOpcode() == Opcode::GetCarryFromOp);
|
|
value.GetInst()->carry_inst = nullptr;
|
|
break;
|
|
case Opcode::GetOverflowFromOp:
|
|
ASSERT(value.GetInst()->overflow_inst->GetOpcode() == Opcode::GetOverflowFromOp);
|
|
value.GetInst()->overflow_inst = nullptr;
|
|
break;
|
|
case Opcode::GetGEFromOp:
|
|
ASSERT(value.GetInst()->ge_inst->GetOpcode() == Opcode::GetGEFromOp);
|
|
value.GetInst()->ge_inst = nullptr;
|
|
break;
|
|
case Opcode::GetNZCVFromOp:
|
|
ASSERT(value.GetInst()->nzcv_inst->GetOpcode() == Opcode::GetNZCVFromOp);
|
|
value.GetInst()->nzcv_inst = nullptr;
|
|
break;
|
|
case Opcode::GetUpperFromOp:
|
|
ASSERT(value.GetInst()->upper_inst->GetOpcode() == Opcode::GetUpperFromOp);
|
|
value.GetInst()->upper_inst = nullptr;
|
|
break;
|
|
case Opcode::GetLowerFromOp:
|
|
ASSERT(value.GetInst()->lower_inst->GetOpcode() == Opcode::GetLowerFromOp);
|
|
value.GetInst()->lower_inst = nullptr;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
} // namespace Dynarmic::IR
|