764 lines
28 KiB
C++
764 lines
28 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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namespace Dynarmic::A32 {
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static ExtReg ToExtReg(bool sz, size_t base, bool bit) {
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if (sz) {
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return static_cast<ExtReg>(static_cast<size_t>(ExtReg::D0) + base + (bit ? 16 : 0));
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} else {
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return static_cast<ExtReg>(static_cast<size_t>(ExtReg::S0) + (base << 1) + (bit ? 1 : 0));
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}
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}
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template <typename FnT>
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bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn) {
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// VFP register banks are 8 single-precision registers in size.
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const size_t register_bank_size = sz ? 4 : 8;
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if (!ir.current_location.FPSCR().Stride()) {
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return UnpredictableInstruction();
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}
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size_t vector_length = ir.current_location.FPSCR().Len();
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size_t vector_stride = *ir.current_location.FPSCR().Stride();
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// Unpredictable case
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if (vector_stride * vector_length > register_bank_size) {
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return UnpredictableInstruction();
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}
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// Scalar case
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if (vector_length == 1) {
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if (vector_stride != 1)
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return UnpredictableInstruction();
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fn(d, n, m);
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return true;
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}
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// The VFP register file is divided into banks each containing:
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// * eight single-precision registers, or
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// * four double-precision reigsters.
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// VFP vector instructions access these registers in a circular manner.
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const auto bank_increment = [register_bank_size](ExtReg reg, size_t stride) -> ExtReg {
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size_t reg_number = static_cast<size_t>(reg);
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size_t bank_index = reg_number % register_bank_size;
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size_t bank_start = reg_number - bank_index;
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size_t next_reg_number = bank_start + ((bank_index + stride) % register_bank_size);
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return static_cast<ExtReg>(next_reg_number);
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};
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// The first and fifth banks in the register file are scalar banks.
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// All the other banks are vector banks.
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const auto belongs_to_scalar_bank = [](ExtReg reg) -> bool {
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return (reg >= ExtReg::D0 && reg <= ExtReg::D3)
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|| (reg >= ExtReg::D16 && reg <= ExtReg::D19)
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|| (reg >= ExtReg::S0 && reg <= ExtReg::S7);
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};
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const bool d_is_scalar = belongs_to_scalar_bank(d);
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const bool m_is_scalar = belongs_to_scalar_bank(m);
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if (d_is_scalar) {
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// If destination register is in a scalar bank, the operands and results are all scalars.
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vector_length = 1;
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}
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for (size_t i = 0; i < vector_length; i++) {
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fn(d, n, m);
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d = bank_increment(d, vector_stride);
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n = bank_increment(n, vector_stride);
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if (!m_is_scalar)
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m = bank_increment(m, vector_stride);
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}
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return true;
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}
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template <typename FnT>
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bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, const FnT& fn) {
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return EmitVfpVectorOperation(sz, d, ExtReg::S0, m, [fn](ExtReg d, ExtReg, ExtReg m){
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fn(d, m);
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});
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}
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bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VADD.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPAdd(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VSUB.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPSub(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMUL.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPMul(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMLA.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = ir.FPAdd(reg_d, ir.FPMul(reg_n, reg_m, true), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMLS.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = ir.FPAdd(reg_d, ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNMUL.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPNeg(ir.FPMul(reg_n, reg_m, true));
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNMLA.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPNeg(ir.FPMul(reg_n, reg_m, true)), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNMLS.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto reg_d = ir.GetExtendedRegister(d);
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auto result = ir.FPAdd(ir.FPNeg(reg_d), ir.FPMul(reg_n, reg_m, true), true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg n = ToExtReg(sz, Vn, N);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VDIV.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
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auto reg_n = ir.GetExtendedRegister(n);
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPDiv(reg_n, reg_m, true);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D) {
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ExtReg d = ToExtReg(true, Vd, D);
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if (t == Reg::PC)
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return UnpredictableInstruction();
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// VMOV.32 <Dd[0]>, <Rt>
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if (ConditionPassed(cond)) {
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auto reg_d = ir.GetExtendedRegister(d);
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auto reg_t = ir.GetRegister(t);
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auto result = ir.Pack2x32To1x64(reg_t, ir.MostSignificantWord(reg_d).result);
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ir.SetExtendedRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N) {
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ExtReg n = ToExtReg(true, Vn, N);
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if (t == Reg::PC)
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return UnpredictableInstruction();
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// VMOV.32 <Rt>, <Dn[0]>
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if (ConditionPassed(cond)) {
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auto reg_n = ir.GetExtendedRegister(n);
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ir.SetRegister(t, ir.LeastSignificantWord(reg_n));
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N) {
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ExtReg n = ToExtReg(false, Vn, N);
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if (t == Reg::PC)
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return UnpredictableInstruction();
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// VMOV <Sn>, <Rt>
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if (ConditionPassed(cond)) {
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ir.SetExtendedRegister(n, ir.GetRegister(t));
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N) {
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ExtReg n = ToExtReg(false, Vn, N);
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if (t == Reg::PC)
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return UnpredictableInstruction();
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// VMOV <Rt>, <Sn>
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if (ConditionPassed(cond)) {
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ir.SetRegister(t, ir.GetExtendedRegister(n));
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
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ExtReg m = ToExtReg(false, Vm, M);
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if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31)
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return UnpredictableInstruction();
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// VMOV <Sm>, <Sm1>, <Rt>, <Rt2>
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if (ConditionPassed(cond)) {
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ir.SetExtendedRegister(m, ir.GetRegister(t));
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ir.SetExtendedRegister(m+1, ir.GetRegister(t2));
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
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ExtReg m = ToExtReg(false, Vm, M);
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if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31)
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return UnpredictableInstruction();
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if (t == t2)
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return UnpredictableInstruction();
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// VMOV <Rt>, <Rt2>, <Sm>, <Sm1>
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if (ConditionPassed(cond)) {
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ir.SetRegister(t, ir.GetExtendedRegister(m));
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ir.SetRegister(t2, ir.GetExtendedRegister(m+1));
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
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ExtReg m = ToExtReg(true, Vm, M);
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if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31)
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return UnpredictableInstruction();
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// VMOV<c> <Dm>, <Rt>, <Rt2>
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if (ConditionPassed(cond)) {
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auto value = ir.Pack2x32To1x64(ir.GetRegister(t), ir.GetRegister(t2));
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ir.SetExtendedRegister(m, value);
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) {
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ExtReg m = ToExtReg(true, Vm, M);
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if (t == Reg::PC || t2 == Reg::PC || m == ExtReg::S31)
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return UnpredictableInstruction();
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if (t == t2)
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return UnpredictableInstruction();
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// VMOV<c> <Rt>, <Rt2>, <Dm>
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if (ConditionPassed(cond)) {
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auto value = ir.GetExtendedRegister(m);
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ir.SetRegister(t, ir.LeastSignificantWord(value));
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ir.SetRegister(t2, ir.MostSignificantWord(value).result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VMOV.{F32,F64} <{S,D}d>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, m, [this](ExtReg d, ExtReg m) {
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ir.SetExtendedRegister(d, ir.GetExtendedRegister(m));
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VABS.{F32,F64} <{S,D}d>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, m, [this](ExtReg d, ExtReg m) {
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPAbs(reg_m);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNEG.{F32,F64} <{S,D}d>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, m, [this](ExtReg d, ExtReg m) {
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPNeg(reg_m);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VSQRT.{F32,F64} <{S,D}d>, <{S,D}m>
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if (ConditionPassed(cond)) {
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return EmitVfpVectorOperation(sz, d, m, [this](ExtReg d, ExtReg m) {
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auto reg_m = ir.GetExtendedRegister(m);
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auto result = ir.FPSqrt(reg_m);
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ir.SetExtendedRegister(d, result);
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});
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}
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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ExtReg d = ToExtReg(!sz, Vd, D); // Destination is of opposite size to source
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ExtReg m = ToExtReg(sz, Vm, M);
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// VCVT.F64.F32 <Sd> <Dm>
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// VCVT.F32.F64 <Dd> <Sm>
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if (ConditionPassed(cond)) {
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auto reg_m = ir.GetExtendedRegister(m);
|
|
if (sz) {
|
|
auto result = ir.FPDoubleToSingle(reg_m, true);
|
|
ir.SetExtendedRegister(d, result);
|
|
} else {
|
|
auto result = ir.FPSingleToDouble(reg_m, true);
|
|
ir.SetExtendedRegister(d, result);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm) {
|
|
ExtReg d = ToExtReg(sz, Vd, D);
|
|
ExtReg m = ToExtReg(false, Vm, M);
|
|
FP::RoundingMode rounding_mode = ir.current_location.FPSCR().RMode();
|
|
// VCVT.F32.{S32,U32} <Sd>, <Sm>
|
|
// VCVT.F64.{S32,U32} <Sd>, <Dm>
|
|
if (ConditionPassed(cond)) {
|
|
auto reg_m = ir.GetExtendedRegister(m);
|
|
if (sz) {
|
|
auto result = is_signed
|
|
? ir.FPSignedFixedToDouble(reg_m, 0, rounding_mode)
|
|
: ir.FPUnsignedFixedToDouble(reg_m, 0, rounding_mode);
|
|
ir.SetExtendedRegister(d, result);
|
|
} else {
|
|
auto result = is_signed
|
|
? ir.FPSignedFixedToSingle(reg_m, 0, rounding_mode)
|
|
: ir.FPUnsignedFixedToSingle(reg_m, 0, rounding_mode);
|
|
ir.SetExtendedRegister(d, result);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
|
|
ExtReg d = ToExtReg(false, Vd, D);
|
|
ExtReg m = ToExtReg(sz, Vm, M);
|
|
// VCVT{,R}.U32.F32 <Sd>, <Sm>
|
|
// VCVT{,R}.U32.F64 <Sd>, <Dm>
|
|
if (ConditionPassed(cond)) {
|
|
auto reg_m = ir.GetExtendedRegister(m);
|
|
auto result = ir.FPToFixedU32(reg_m, 0, round_towards_zero ? FP::RoundingMode::TowardsZero : ir.current_location.FPSCR().RMode());
|
|
ir.SetExtendedRegister(d, result);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
|
|
ExtReg d = ToExtReg(false, Vd, D);
|
|
ExtReg m = ToExtReg(sz, Vm, M);
|
|
// VCVT{,R}.S32.F32 <Sd>, <Sm>
|
|
// VCVT{,R}.S32.F64 <Sd>, <Dm>
|
|
if (ConditionPassed(cond)) {
|
|
auto reg_m = ir.GetExtendedRegister(m);
|
|
auto result = ir.FPToFixedS32(reg_m, 0, round_towards_zero ? FP::RoundingMode::TowardsZero : ir.current_location.FPSCR().RMode());
|
|
ir.SetExtendedRegister(d, result);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool E, bool M, size_t Vm) {
|
|
ExtReg d = ToExtReg(sz, Vd, D);
|
|
ExtReg m = ToExtReg(sz, Vm, M);
|
|
bool exc_on_qnan = E;
|
|
// VCMP{E}.F32 <Sd>, <Sm>
|
|
// VCMP{E}.F64 <Dd>, <Dm>
|
|
if (ConditionPassed(cond)) {
|
|
auto reg_d = ir.GetExtendedRegister(d);
|
|
auto reg_m = ir.GetExtendedRegister(m);
|
|
auto nzcv = ir.FPCompare(reg_d, reg_m, exc_on_qnan, true);
|
|
ir.SetFpscrNZCV(nzcv);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, bool E) {
|
|
ExtReg d = ToExtReg(sz, Vd, D);
|
|
bool exc_on_qnan = E;
|
|
// VCMP{E}.F32 <Sd>, #0.0
|
|
// VCMP{E}.F64 <Dd>, #0.0
|
|
if (ConditionPassed(cond)) {
|
|
auto reg_d = ir.GetExtendedRegister(d);
|
|
if (sz) {
|
|
auto nzcv = ir.FPCompare(reg_d, ir.Imm64(0), exc_on_qnan, true);
|
|
ir.SetFpscrNZCV(nzcv);
|
|
} else {
|
|
auto nzcv = ir.FPCompare(reg_d, ir.Imm32(0), exc_on_qnan, true);
|
|
ir.SetFpscrNZCV(nzcv);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VMSR(Cond cond, Reg t) {
|
|
if (t == Reg::PC)
|
|
return UnpredictableInstruction();
|
|
|
|
// VMSR FPSCR, <Rt>
|
|
if (ConditionPassed(cond)) {
|
|
ir.PushRSB(ir.current_location.AdvancePC(4)); // TODO: Replace this with a local cache.
|
|
ir.SetFpscr(ir.GetRegister(t));
|
|
ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
|
|
ir.SetTerm(IR::Term::PopRSBHint{});
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VMRS(Cond cond, Reg t) {
|
|
// VMRS <Rt>, FPSCR
|
|
if (ConditionPassed(cond)) {
|
|
if (t == Reg::R15) {
|
|
// This encodes ASPR_nzcv access
|
|
auto nzcv = ir.GetFpscrNZCV();
|
|
ir.SetCpsrNZCV(nzcv);
|
|
} else {
|
|
ir.SetRegister(t, ir.GetFpscr());
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
|
|
const ExtReg d = ToExtReg(sz, Vd, D);
|
|
const size_t regs = sz ? imm8 >> 1 : imm8;
|
|
|
|
if (regs == 0 || RegNumber(d)+regs > 32)
|
|
return UnpredictableInstruction();
|
|
if (sz && regs > 16)
|
|
return UnpredictableInstruction();
|
|
|
|
// VPOP.{F32,F64} <list>
|
|
if (ConditionPassed(cond)) {
|
|
auto address = ir.GetRegister(Reg::SP);
|
|
|
|
for (size_t i = 0; i < regs; ++i) {
|
|
if (sz) {
|
|
auto lo = ir.ReadMemory32(address);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
auto hi = ir.ReadMemory32(address);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
if (ir.current_location.EFlag()) std::swap(lo, hi);
|
|
ir.SetExtendedRegister(d + i, ir.Pack2x32To1x64(lo, hi));
|
|
} else {
|
|
auto res = ir.ReadMemory32(address);
|
|
ir.SetExtendedRegister(d + i, res);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
}
|
|
}
|
|
|
|
ir.SetRegister(Reg::SP, address);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
|
|
u32 imm32 = imm8 << 2;
|
|
const ExtReg d = ToExtReg(sz, Vd, D);
|
|
const size_t regs = sz ? imm8 >> 1 : imm8;
|
|
|
|
if (regs == 0 || RegNumber(d)+regs > 32)
|
|
return UnpredictableInstruction();
|
|
if (sz && regs > 16)
|
|
return UnpredictableInstruction();
|
|
|
|
// VPUSH.{F32,F64} <list>
|
|
if (ConditionPassed(cond)) {
|
|
auto address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(imm32));
|
|
ir.SetRegister(Reg::SP, address);
|
|
|
|
for (size_t i = 0; i < regs; ++i) {
|
|
if (sz) {
|
|
const auto reg_d = ir.GetExtendedRegister(d + i);
|
|
auto lo = ir.LeastSignificantWord(reg_d);
|
|
auto hi = ir.MostSignificantWord(reg_d).result;
|
|
if (ir.current_location.EFlag()) std::swap(lo, hi);
|
|
ir.WriteMemory32(address, lo);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
ir.WriteMemory32(address, hi);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
} else {
|
|
ir.WriteMemory32(address, ir.GetExtendedRegister(d + i));
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
}
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
|
|
u32 imm32 = imm8 << 2;
|
|
ExtReg d = ToExtReg(sz, Vd, D);
|
|
// VLDR <{S,D}d>, [<Rn>, #+/-<imm32>]
|
|
if (ConditionPassed(cond)) {
|
|
auto base = n == Reg::PC ? ir.Imm32(ir.AlignPC(4)) : ir.GetRegister(n);
|
|
auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
|
|
if (sz) {
|
|
auto lo = ir.ReadMemory32(address);
|
|
auto hi = ir.ReadMemory32(ir.Add(address, ir.Imm32(4)));
|
|
if (ir.current_location.EFlag()) std::swap(lo, hi);
|
|
ir.SetExtendedRegister(d, ir.Pack2x32To1x64(lo, hi));
|
|
} else {
|
|
ir.SetExtendedRegister(d, ir.ReadMemory32(address));
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
|
|
u32 imm32 = imm8 << 2;
|
|
ExtReg d = ToExtReg(sz, Vd, D);
|
|
// VSTR <{S,D}d>, [<Rn>, #+/-<imm32>]
|
|
if (ConditionPassed(cond)) {
|
|
auto base = n == Reg::PC ? ir.Imm32(ir.AlignPC(4)) : ir.GetRegister(n);
|
|
auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
|
|
if (sz) {
|
|
auto reg_d = ir.GetExtendedRegister(d);
|
|
auto lo = ir.LeastSignificantWord(reg_d);
|
|
auto hi = ir.MostSignificantWord(reg_d).result;
|
|
if (ir.current_location.EFlag()) std::swap(lo, hi);
|
|
ir.WriteMemory32(address, lo);
|
|
ir.WriteMemory32(ir.Add(address, ir.Imm32(4)), hi);
|
|
} else {
|
|
ir.WriteMemory32(address, ir.GetExtendedRegister(d));
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
|
if (!p && !u && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p == u && w)
|
|
return arm_UDF();
|
|
if (n == Reg::PC && w)
|
|
return UnpredictableInstruction();
|
|
|
|
ExtReg d = ToExtReg(true, Vd, D);
|
|
u32 imm32 = imm8 << 2;
|
|
size_t regs = imm8 / 2;
|
|
|
|
if (regs == 0 || regs > 16 || A32::RegNumber(d)+regs > 32)
|
|
return UnpredictableInstruction();
|
|
|
|
// VSTM<mode>.F64 <Rn>{!}, <list of double registers>
|
|
if (ConditionPassed(cond)) {
|
|
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
|
|
if (w)
|
|
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
|
|
for (size_t i = 0; i < regs; i++) {
|
|
auto value = ir.GetExtendedRegister(d + i);
|
|
auto word1 = ir.LeastSignificantWord(value);
|
|
auto word2 = ir.MostSignificantWord(value).result;
|
|
if (ir.current_location.EFlag()) std::swap(word1, word2);
|
|
ir.WriteMemory32(address, word1);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
ir.WriteMemory32(address, word2);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
|
if (!p && !u && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p == u && w)
|
|
return arm_UDF();
|
|
if (n == Reg::PC && w)
|
|
return UnpredictableInstruction();
|
|
|
|
ExtReg d = ToExtReg(false, Vd, D);
|
|
u32 imm32 = imm8 << 2;
|
|
size_t regs = imm8;
|
|
|
|
if (regs == 0 || A32::RegNumber(d)+regs > 32)
|
|
return UnpredictableInstruction();
|
|
|
|
// VSTM<mode>.F32 <Rn>{!}, <list of single registers>
|
|
if (ConditionPassed(cond)) {
|
|
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
|
|
if (w)
|
|
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
|
|
for (size_t i = 0; i < regs; i++) {
|
|
auto word = ir.GetExtendedRegister(d + i);
|
|
ir.WriteMemory32(address, word);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
|
if (!p && !u && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p == u && w)
|
|
return arm_UDF();
|
|
if (n == Reg::PC && w)
|
|
return UnpredictableInstruction();
|
|
|
|
ExtReg d = ToExtReg(true, Vd, D);
|
|
u32 imm32 = imm8 << 2;
|
|
size_t regs = imm8 / 2;
|
|
|
|
if (regs == 0 || regs > 16 || A32::RegNumber(d)+regs > 32)
|
|
return UnpredictableInstruction();
|
|
|
|
// VLDM<mode>.F64 <Rn>{!}, <list of double registers>
|
|
if (ConditionPassed(cond)) {
|
|
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
|
|
if (w)
|
|
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
|
|
for (size_t i = 0; i < regs; i++) {
|
|
auto word1 = ir.ReadMemory32(address);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
auto word2 = ir.ReadMemory32(address);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
if (ir.current_location.EFlag()) std::swap(word1, word2);
|
|
ir.SetExtendedRegister(d + i, ir.Pack2x32To1x64(word1, word2));
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
|
if (!p && !u && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p && !w)
|
|
ASSERT_MSG(false, "Decode error");
|
|
if (p == u && w)
|
|
return arm_UDF();
|
|
if (n == Reg::PC && w)
|
|
return UnpredictableInstruction();
|
|
|
|
ExtReg d = ToExtReg(false, Vd, D);
|
|
u32 imm32 = imm8 << 2;
|
|
size_t regs = imm8;
|
|
|
|
if (regs == 0 || A32::RegNumber(d)+regs > 32)
|
|
return UnpredictableInstruction();
|
|
|
|
// VLDM<mode>.F32 <Rn>{!}, <list of single registers>
|
|
if (ConditionPassed(cond)) {
|
|
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
|
|
if (w)
|
|
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
|
|
for (size_t i = 0; i < regs; i++) {
|
|
auto word = ir.ReadMemory32(address);
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
ir.SetExtendedRegister(d + i, word);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
} // namespace Dynarmic::A32
|