d69fceec55
This'll make it slightly nicer to do basic constant folding for 32-bit and 64-bit variants of the same IR opcode type. By that, I mean it's possible to inspect immediate values without a bunch of conditional checks beforehand to verify that it's possible to call GetU32() or GetU64, etc.
675 lines
21 KiB
C++
675 lines
21 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include <numeric>
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#include <utility>
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#include <fmt/ostream.h>
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#include <xbyak.h>
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#include "backend/x64/abi.h"
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#include "backend/x64/reg_alloc.h"
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#include "common/assert.h"
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namespace Dynarmic::BackendX64 {
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#define MAYBE_AVX(OPCODE, ...) \
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[&] { \
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) { \
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code.v##OPCODE(__VA_ARGS__); \
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} else { \
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code.OPCODE(__VA_ARGS__); \
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} \
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}()
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static bool CanExchange(HostLoc a, HostLoc b) {
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return HostLocIsGPR(a) && HostLocIsGPR(b);
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}
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// Minimum number of bits required to represent a type
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static size_t GetBitWidth(IR::Type type) {
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switch (type) {
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case IR::Type::A32Reg:
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case IR::Type::A32ExtReg:
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case IR::Type::A64Reg:
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case IR::Type::A64Vec:
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case IR::Type::CoprocInfo:
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case IR::Type::Cond:
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case IR::Type::Void:
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case IR::Type::Table:
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ASSERT_MSG(false, "Type {} cannot be represented at runtime", type);
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return 0;
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case IR::Type::Opaque:
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ASSERT_MSG(false, "Not a concrete type");
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return 0;
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case IR::Type::U1:
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return 8;
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case IR::Type::U8:
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return 8;
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case IR::Type::U16:
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return 16;
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case IR::Type::U32:
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return 32;
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case IR::Type::U64:
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return 64;
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case IR::Type::U128:
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return 128;
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case IR::Type::NZCVFlags:
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return 32; // TODO: Update to 16 when flags optimization is done
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}
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UNREACHABLE();
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return 0;
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}
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static bool IsValuelessType(IR::Type type) {
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switch (type) {
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case IR::Type::Table:
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return true;
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default:
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return false;
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}
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}
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bool HostLocInfo::IsLocked() const {
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return is_being_used_count > 0;
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}
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bool HostLocInfo::IsEmpty() const {
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return is_being_used_count == 0 && values.empty();
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}
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bool HostLocInfo::IsLastUse() const {
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return is_being_used_count == 0 && current_references == 1 && accumulated_uses + 1 == total_uses;
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}
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void HostLocInfo::ReadLock() {
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ASSERT(!is_scratch);
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is_being_used_count++;
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}
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void HostLocInfo::WriteLock() {
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ASSERT(is_being_used_count == 0);
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is_being_used_count++;
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is_scratch = true;
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}
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void HostLocInfo::AddArgReference() {
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current_references++;
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ASSERT(accumulated_uses + current_references <= total_uses);
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}
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void HostLocInfo::ReleaseOne() {
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is_being_used_count--;
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is_scratch = false;
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if (current_references == 0)
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return;
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accumulated_uses++;
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current_references--;
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if (current_references == 0)
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ReleaseAll();
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}
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void HostLocInfo::ReleaseAll() {
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accumulated_uses += current_references;
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current_references = 0;
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ASSERT(total_uses == std::accumulate(values.begin(), values.end(), size_t(0), [](size_t sum, IR::Inst* inst) { return sum + inst->UseCount(); }));
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if (total_uses == accumulated_uses) {
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values.clear();
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accumulated_uses = 0;
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total_uses = 0;
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max_bit_width = 0;
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}
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is_being_used_count = 0;
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is_scratch = false;
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}
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bool HostLocInfo::ContainsValue(const IR::Inst* inst) const {
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return std::find(values.begin(), values.end(), inst) != values.end();
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}
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size_t HostLocInfo::GetMaxBitWidth() const {
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return max_bit_width;
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}
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void HostLocInfo::AddValue(IR::Inst* inst) {
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values.push_back(inst);
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total_uses += inst->UseCount();
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max_bit_width = std::max(max_bit_width, GetBitWidth(inst->GetType()));
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}
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IR::Type Argument::GetType() const {
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return value.GetType();
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}
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bool Argument::IsImmediate() const {
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return value.IsImmediate();
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}
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bool Argument::IsVoid() const {
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return GetType() == IR::Type::Void;
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}
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bool Argument::FitsInImmediateU32() const {
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if (!IsImmediate())
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return false;
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const u64 imm = value.GetImmediateAsU64();
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return imm < 0x100000000;
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}
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bool Argument::FitsInImmediateS32() const {
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if (!IsImmediate())
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return false;
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const s64 imm = static_cast<s64>(value.GetImmediateAsU64());
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return -s64(0x80000000) <= imm && imm <= s64(0x7FFFFFFF);
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}
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bool Argument::GetImmediateU1() const {
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return value.GetU1();
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}
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u8 Argument::GetImmediateU8() const {
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const u64 imm = value.GetImmediateAsU64();
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ASSERT(imm < 0x100);
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return u8(imm);
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}
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u16 Argument::GetImmediateU16() const {
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const u64 imm = value.GetImmediateAsU64();
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ASSERT(imm < 0x10000);
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return u16(imm);
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}
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u32 Argument::GetImmediateU32() const {
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const u64 imm = value.GetImmediateAsU64();
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ASSERT(imm < 0x100000000);
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return u32(imm);
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}
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u64 Argument::GetImmediateS32() const {
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ASSERT(FitsInImmediateS32());
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return value.GetImmediateAsU64();
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}
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u64 Argument::GetImmediateU64() const {
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return value.GetImmediateAsU64();
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}
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IR::Cond Argument::GetImmediateCond() const {
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ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
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return value.GetCond();
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}
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bool Argument::IsInGpr() const {
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if (IsImmediate())
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return false;
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return HostLocIsGPR(*reg_alloc.ValueLocation(value.GetInst()));
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}
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bool Argument::IsInXmm() const {
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if (IsImmediate())
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return false;
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return HostLocIsXMM(*reg_alloc.ValueLocation(value.GetInst()));
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}
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bool Argument::IsInMemory() const {
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if (IsImmediate())
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return false;
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return HostLocIsSpill(*reg_alloc.ValueLocation(value.GetInst()));
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}
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RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
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ArgumentInfo ret = {Argument{*this}, Argument{*this}, Argument{*this}, Argument{*this}};
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for (size_t i = 0; i < inst->NumArgs(); i++) {
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const IR::Value& arg = inst->GetArg(i);
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ret[i].value = arg;
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if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
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ASSERT_MSG(ValueLocation(arg.GetInst()), "argument must already been defined");
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LocInfo(*ValueLocation(arg.GetInst())).AddArgReference();
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}
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}
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return ret;
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}
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Xbyak::Reg64 RegAlloc::UseGpr(Argument& arg) {
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ASSERT(!arg.allocated);
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arg.allocated = true;
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return HostLocToReg64(UseImpl(arg.value, any_gpr));
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}
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Xbyak::Xmm RegAlloc::UseXmm(Argument& arg) {
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ASSERT(!arg.allocated);
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arg.allocated = true;
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return HostLocToXmm(UseImpl(arg.value, any_xmm));
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}
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OpArg RegAlloc::UseOpArg(Argument& arg) {
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return UseGpr(arg);
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}
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void RegAlloc::Use(Argument& arg, HostLoc host_loc) {
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ASSERT(!arg.allocated);
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arg.allocated = true;
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UseImpl(arg.value, {host_loc});
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}
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Xbyak::Reg64 RegAlloc::UseScratchGpr(Argument& arg) {
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ASSERT(!arg.allocated);
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arg.allocated = true;
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return HostLocToReg64(UseScratchImpl(arg.value, any_gpr));
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}
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Xbyak::Xmm RegAlloc::UseScratchXmm(Argument& arg) {
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ASSERT(!arg.allocated);
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arg.allocated = true;
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return HostLocToXmm(UseScratchImpl(arg.value, any_xmm));
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}
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void RegAlloc::UseScratch(Argument& arg, HostLoc host_loc) {
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ASSERT(!arg.allocated);
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arg.allocated = true;
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UseScratchImpl(arg.value, {host_loc});
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}
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void RegAlloc::DefineValue(IR::Inst* inst, const Xbyak::Reg& reg) {
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ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
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HostLoc hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
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DefineValueImpl(inst, hostloc);
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}
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void RegAlloc::DefineValue(IR::Inst* inst, Argument& arg) {
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ASSERT(!arg.allocated);
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arg.allocated = true;
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DefineValueImpl(inst, arg.value);
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}
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void RegAlloc::Release(const Xbyak::Reg& reg) {
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ASSERT(reg.getKind() == Xbyak::Operand::XMM || reg.getKind() == Xbyak::Operand::REG);
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const HostLoc hostloc = static_cast<HostLoc>(reg.getIdx() + static_cast<size_t>(reg.getKind() == Xbyak::Operand::XMM ? HostLoc::XMM0 : HostLoc::RAX));
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LocInfo(hostloc).ReleaseOne();
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}
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Xbyak::Reg64 RegAlloc::ScratchGpr(HostLocList desired_locations) {
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return HostLocToReg64(ScratchImpl(desired_locations));
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}
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Xbyak::Xmm RegAlloc::ScratchXmm(HostLocList desired_locations) {
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return HostLocToXmm(ScratchImpl(desired_locations));
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}
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HostLoc RegAlloc::UseImpl(IR::Value use_value, HostLocList desired_locations) {
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if (use_value.IsImmediate()) {
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return LoadImmediate(use_value, ScratchImpl(desired_locations));
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}
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const IR::Inst* use_inst = use_value.GetInst();
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const HostLoc current_location = *ValueLocation(use_inst);
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const size_t max_bit_width = LocInfo(current_location).GetMaxBitWidth();
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const bool can_use_current_location = std::find(desired_locations.begin(), desired_locations.end(), current_location) != desired_locations.end();
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if (can_use_current_location) {
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LocInfo(current_location).ReadLock();
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return current_location;
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}
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if (LocInfo(current_location).IsLocked()) {
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return UseScratchImpl(use_value, desired_locations);
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}
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const HostLoc destination_location = SelectARegister(desired_locations);
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if (max_bit_width > HostLocBitWidth(destination_location)) {
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return UseScratchImpl(use_value, desired_locations);
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} else if (CanExchange(destination_location, current_location)) {
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Exchange(destination_location, current_location);
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} else {
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MoveOutOfTheWay(destination_location);
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Move(destination_location, current_location);
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}
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LocInfo(destination_location).ReadLock();
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return destination_location;
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}
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HostLoc RegAlloc::UseScratchImpl(IR::Value use_value, HostLocList desired_locations) {
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if (use_value.IsImmediate()) {
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return LoadImmediate(use_value, ScratchImpl(desired_locations));
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}
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const IR::Inst* use_inst = use_value.GetInst();
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const HostLoc current_location = *ValueLocation(use_inst);
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const size_t bit_width = GetBitWidth(use_inst->GetType());
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const bool can_use_current_location = std::find(desired_locations.begin(), desired_locations.end(), current_location) != desired_locations.end();
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if (can_use_current_location && !LocInfo(current_location).IsLocked()) {
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if (!LocInfo(current_location).IsLastUse()) {
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MoveOutOfTheWay(current_location);
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}
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LocInfo(current_location).WriteLock();
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return current_location;
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}
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const HostLoc destination_location = SelectARegister(desired_locations);
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MoveOutOfTheWay(destination_location);
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CopyToScratch(bit_width, destination_location, current_location);
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LocInfo(destination_location).WriteLock();
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return destination_location;
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}
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HostLoc RegAlloc::ScratchImpl(HostLocList desired_locations) {
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HostLoc location = SelectARegister(desired_locations);
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MoveOutOfTheWay(location);
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LocInfo(location).WriteLock();
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return location;
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}
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void RegAlloc::HostCall(IR::Inst* result_def, boost::optional<Argument&> arg0, boost::optional<Argument&> arg1, boost::optional<Argument&> arg2, boost::optional<Argument&> arg3) {
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constexpr size_t args_count = 4;
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constexpr std::array<HostLoc, args_count> args_hostloc = { ABI_PARAM1, ABI_PARAM2, ABI_PARAM3, ABI_PARAM4 };
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const std::array<boost::optional<Argument&>, args_count> args = { arg0, arg1, arg2, arg3 };
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static const std::vector<HostLoc> other_caller_save = [args_hostloc]() {
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std::vector<HostLoc> ret(ABI_ALL_CALLER_SAVE.begin(), ABI_ALL_CALLER_SAVE.end());
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ret.erase(std::find(ret.begin(), ret.end(), ABI_RETURN));
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for (auto hostloc : args_hostloc)
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ret.erase(std::find(ret.begin(), ret.end(), hostloc));
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return ret;
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}();
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ScratchGpr({ABI_RETURN});
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if (result_def) {
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DefineValueImpl(result_def, ABI_RETURN);
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}
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for (size_t i = 0; i < args_count; i++) {
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if (args[i]) {
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UseScratch(*args[i], args_hostloc[i]);
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#if defined(__llvm__) && !defined(_WIN32)
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// LLVM puts the burden of zero-extension of 8 and 16 bit values on the caller instead of the callee
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Xbyak::Reg64 reg = HostLocToReg64(args_hostloc[i]);
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switch (args[i]->GetType()) {
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case IR::Type::U8:
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code.movzx(reg.cvt32(), reg.cvt8());
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break;
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case IR::Type::U16:
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code.movzx(reg.cvt32(), reg.cvt16());
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break;
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default:
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break; // Nothing needs to be done
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}
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#endif
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}
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}
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for (size_t i = 0; i < args_count; i++) {
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if (!args[i]) {
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// TODO: Force spill
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ScratchGpr({args_hostloc[i]});
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}
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}
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for (HostLoc caller_saved : other_caller_save) {
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ScratchImpl({caller_saved});
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}
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}
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void RegAlloc::EndOfAllocScope() {
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for (auto& iter : hostloc_info) {
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iter.ReleaseAll();
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}
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}
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void RegAlloc::AssertNoMoreUses() {
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ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i) { return i.IsEmpty(); }));
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}
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HostLoc RegAlloc::SelectARegister(HostLocList desired_locations) const {
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std::vector<HostLoc> candidates = desired_locations;
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// Find all locations that have not been allocated..
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auto allocated_locs = std::partition(candidates.begin(), candidates.end(), [this](auto loc){
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return !this->LocInfo(loc).IsLocked();
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});
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candidates.erase(allocated_locs, candidates.end());
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ASSERT_MSG(!candidates.empty(), "All candidate registers have already been allocated");
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// Selects the best location out of the available locations.
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// TODO: Actually do LRU or something. Currently we just try to pick something without a value if possible.
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std::partition(candidates.begin(), candidates.end(), [this](auto loc){
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return this->LocInfo(loc).IsEmpty();
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});
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return candidates.front();
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}
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boost::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const {
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for (size_t i = 0; i < hostloc_info.size(); i++)
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if (hostloc_info[i].ContainsValue(value))
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return static_cast<HostLoc>(i);
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return boost::none;
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}
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void RegAlloc::DefineValueImpl(IR::Inst* def_inst, HostLoc host_loc) {
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ASSERT_MSG(!ValueLocation(def_inst), "def_inst has already been defined");
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LocInfo(host_loc).AddValue(def_inst);
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}
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void RegAlloc::DefineValueImpl(IR::Inst* def_inst, const IR::Value& use_inst) {
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ASSERT_MSG(!ValueLocation(def_inst), "def_inst has already been defined");
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if (use_inst.IsImmediate()) {
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HostLoc location = ScratchImpl(any_gpr);
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DefineValueImpl(def_inst, location);
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LoadImmediate(use_inst, location);
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return;
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}
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ASSERT_MSG(ValueLocation(use_inst.GetInst()), "use_inst must already be defined");
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HostLoc location = *ValueLocation(use_inst.GetInst());
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DefineValueImpl(def_inst, location);
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}
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HostLoc RegAlloc::LoadImmediate(IR::Value imm, HostLoc host_loc) {
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ASSERT_MSG(imm.IsImmediate(), "imm is not an immediate");
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if (HostLocIsGPR(host_loc)) {
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const Xbyak::Reg64 reg = HostLocToReg64(host_loc);
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const u64 imm_value = imm.GetImmediateAsU64();
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if (imm_value == 0)
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code.xor_(reg.cvt32(), reg.cvt32());
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else
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code.mov(reg, imm_value);
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return host_loc;
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}
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if (HostLocIsXMM(host_loc)) {
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const Xbyak::Xmm reg = HostLocToXmm(host_loc);
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const u64 imm_value = imm.GetImmediateAsU64();
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if (imm_value == 0)
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MAYBE_AVX(xorps, reg, reg);
|
|
else
|
|
MAYBE_AVX(movaps, reg, code.MConst(code.xword, imm_value));
|
|
return host_loc;
|
|
}
|
|
|
|
UNREACHABLE();
|
|
}
|
|
|
|
void RegAlloc::Move(HostLoc to, HostLoc from) {
|
|
const size_t bit_width = LocInfo(from).GetMaxBitWidth();
|
|
|
|
ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
|
|
ASSERT(bit_width <= HostLocBitWidth(to));
|
|
|
|
if (LocInfo(from).IsEmpty()) {
|
|
return;
|
|
}
|
|
|
|
EmitMove(bit_width, to, from);
|
|
|
|
LocInfo(to) = std::exchange(LocInfo(from), {});
|
|
}
|
|
|
|
void RegAlloc::CopyToScratch(size_t bit_width, HostLoc to, HostLoc from) {
|
|
ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsEmpty());
|
|
|
|
EmitMove(bit_width, to, from);
|
|
}
|
|
|
|
void RegAlloc::Exchange(HostLoc a, HostLoc b) {
|
|
ASSERT(!LocInfo(a).IsLocked() && !LocInfo(b).IsLocked());
|
|
ASSERT(LocInfo(a).GetMaxBitWidth() <= HostLocBitWidth(b));
|
|
ASSERT(LocInfo(b).GetMaxBitWidth() <= HostLocBitWidth(a));
|
|
|
|
if (LocInfo(a).IsEmpty()) {
|
|
Move(a, b);
|
|
return;
|
|
}
|
|
|
|
if (LocInfo(b).IsEmpty()) {
|
|
Move(b, a);
|
|
return;
|
|
}
|
|
|
|
EmitExchange(a, b);
|
|
|
|
std::swap(LocInfo(a), LocInfo(b));
|
|
}
|
|
|
|
void RegAlloc::MoveOutOfTheWay(HostLoc reg) {
|
|
ASSERT(!LocInfo(reg).IsLocked());
|
|
if (!LocInfo(reg).IsEmpty()) {
|
|
SpillRegister(reg);
|
|
}
|
|
}
|
|
|
|
void RegAlloc::SpillRegister(HostLoc loc) {
|
|
ASSERT_MSG(HostLocIsRegister(loc), "Only registers can be spilled");
|
|
ASSERT_MSG(!LocInfo(loc).IsEmpty(), "There is no need to spill unoccupied registers");
|
|
ASSERT_MSG(!LocInfo(loc).IsLocked(), "Registers that have been allocated must not be spilt");
|
|
|
|
HostLoc new_loc = FindFreeSpill();
|
|
Move(new_loc, loc);
|
|
}
|
|
|
|
HostLoc RegAlloc::FindFreeSpill() const {
|
|
for (size_t i = static_cast<size_t>(HostLoc::FirstSpill); i < hostloc_info.size(); i++) {
|
|
HostLoc loc = static_cast<HostLoc>(i);
|
|
if (LocInfo(loc).IsEmpty())
|
|
return loc;
|
|
}
|
|
|
|
ASSERT_MSG(false, "All spill locations are full");
|
|
}
|
|
|
|
HostLocInfo& RegAlloc::LocInfo(HostLoc loc) {
|
|
ASSERT(loc != HostLoc::RSP && loc != HostLoc::R15);
|
|
return hostloc_info[static_cast<size_t>(loc)];
|
|
}
|
|
|
|
const HostLocInfo& RegAlloc::LocInfo(HostLoc loc) const {
|
|
ASSERT(loc != HostLoc::RSP && loc != HostLoc::R15);
|
|
return hostloc_info[static_cast<size_t>(loc)];
|
|
}
|
|
|
|
void RegAlloc::EmitMove(size_t bit_width, HostLoc to, HostLoc from) {
|
|
if (HostLocIsXMM(to) && HostLocIsXMM(from)) {
|
|
MAYBE_AVX(movaps, HostLocToXmm(to), HostLocToXmm(from));
|
|
} else if (HostLocIsGPR(to) && HostLocIsGPR(from)) {
|
|
ASSERT(bit_width != 128);
|
|
if (bit_width == 64) {
|
|
code.mov(HostLocToReg64(to), HostLocToReg64(from));
|
|
} else {
|
|
code.mov(HostLocToReg64(to).cvt32(), HostLocToReg64(from).cvt32());
|
|
}
|
|
} else if (HostLocIsXMM(to) && HostLocIsGPR(from)) {
|
|
ASSERT(bit_width != 128);
|
|
if (bit_width == 64) {
|
|
MAYBE_AVX(movq, HostLocToXmm(to), HostLocToReg64(from));
|
|
} else {
|
|
MAYBE_AVX(movd, HostLocToXmm(to), HostLocToReg64(from).cvt32());
|
|
}
|
|
} else if (HostLocIsGPR(to) && HostLocIsXMM(from)) {
|
|
ASSERT(bit_width != 128);
|
|
if (bit_width == 64) {
|
|
MAYBE_AVX(movq, HostLocToReg64(to), HostLocToXmm(from));
|
|
} else {
|
|
MAYBE_AVX(movd, HostLocToReg64(to).cvt32(), HostLocToXmm(from));
|
|
}
|
|
} else if (HostLocIsXMM(to) && HostLocIsSpill(from)) {
|
|
Xbyak::Address spill_addr = spill_to_addr(from);
|
|
ASSERT(spill_addr.getBit() >= bit_width);
|
|
switch (bit_width) {
|
|
case 128:
|
|
MAYBE_AVX(movaps, HostLocToXmm(to), spill_addr);
|
|
break;
|
|
case 64:
|
|
MAYBE_AVX(movsd, HostLocToXmm(to), spill_addr);
|
|
break;
|
|
case 32:
|
|
case 16:
|
|
case 8:
|
|
MAYBE_AVX(movss, HostLocToXmm(to), spill_addr);
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
} else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
|
|
Xbyak::Address spill_addr = spill_to_addr(to);
|
|
ASSERT(spill_addr.getBit() >= bit_width);
|
|
switch (bit_width) {
|
|
case 128:
|
|
MAYBE_AVX(movaps, spill_addr, HostLocToXmm(from));
|
|
break;
|
|
case 64:
|
|
MAYBE_AVX(movsd, spill_addr, HostLocToXmm(from));
|
|
break;
|
|
case 32:
|
|
case 16:
|
|
case 8:
|
|
MAYBE_AVX(movss, spill_addr, HostLocToXmm(from));
|
|
break;
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
} else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
|
|
ASSERT(bit_width != 128);
|
|
if (bit_width == 64) {
|
|
code.mov(HostLocToReg64(to), spill_to_addr(from));
|
|
} else {
|
|
code.mov(HostLocToReg64(to).cvt32(), spill_to_addr(from));
|
|
}
|
|
} else if (HostLocIsSpill(to) && HostLocIsGPR(from)) {
|
|
ASSERT(bit_width != 128);
|
|
if (bit_width == 64) {
|
|
code.mov(spill_to_addr(to), HostLocToReg64(from));
|
|
} else {
|
|
code.mov(spill_to_addr(to), HostLocToReg64(from).cvt32());
|
|
}
|
|
} else {
|
|
ASSERT_MSG(false, "Invalid RegAlloc::EmitMove");
|
|
}
|
|
}
|
|
|
|
void RegAlloc::EmitExchange(HostLoc a, HostLoc b) {
|
|
if (HostLocIsGPR(a) && HostLocIsGPR(b)) {
|
|
code.xchg(HostLocToReg64(a), HostLocToReg64(b));
|
|
} else if (HostLocIsXMM(a) && HostLocIsXMM(b)) {
|
|
ASSERT_MSG(false, "Check your code: Exchanging XMM registers is unnecessary");
|
|
} else {
|
|
ASSERT_MSG(false, "Invalid RegAlloc::EmitExchange");
|
|
}
|
|
}
|
|
|
|
} // namespace Dynarmic::BackendX64
|