110 lines
3.8 KiB
C++
110 lines
3.8 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include <array>
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#include "common/common_types.h"
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#include "common/intrusive_list.h"
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#include "frontend/ir/opcodes.h"
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#include "frontend/ir/value.h"
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namespace Dynarmic {
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namespace IR {
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/**
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* A representation of a microinstruction. A single ARM/Thumb instruction may be
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* converted into zero or more microinstructions.
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*/
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class Inst final : public Common::IntrusiveListNode<Inst> {
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public:
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explicit Inst(Opcode op) : op(op) {}
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/// Determines whether or not this instruction performs an arithmetic shift.
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bool IsArithmeticShift() const;
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/// Determines whether or not this instruction performs a logical shift.
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bool IsLogicalShift() const;
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/// Determines whether or not this instruction performs a circular shift.
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bool IsCircularShift() const;
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/// Determines whether or not this instruction performs any kind of shift.
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bool IsShift() const;
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/// Determines whether or not this instruction performs a shared memory read.
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bool IsSharedMemoryRead() const;
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/// Determines whether or not this instruction performs a shared memory write.
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bool IsSharedMemoryWrite() const;
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/// Determines whether or not this instruction performs a shared memory read or write.
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bool IsSharedMemoryReadOrWrite() const;
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/// Determines whether or not this instruction performs an atomic memory write.
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bool IsExclusiveMemoryWrite() const;
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/// Determines whether or not this instruction performs any kind of memory read.
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bool IsMemoryRead() const;
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/// Determines whether or not this instruction performs any kind of memory write.
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bool IsMemoryWrite() const;
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/// Determines whether or not this instruction performs any kind of memory access.
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bool IsMemoryReadOrWrite() const;
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/// Determines whether or not this instruction reads from the CPSR.
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bool ReadsFromCPSR() const;
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/// Determines whether or not this instruction writes to the CPSR.
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bool WritesToCPSR() const;
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/// Determines whether or not this instruction reads from a core register.
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bool ReadsFromCoreRegister() const;
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/// Determines whether or not this instruction writes to a core register.
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bool WritesToCoreRegister() const;
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/// Determines whether or not this instruction reads from the FPSCR.
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bool ReadsFromFPSCR() const;
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/// Determines whether or not this instruction writes to the FPSCR.
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bool WritesToFPSCR() const;
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/// Determines whether or not this instruction alters memory-exclusivity.
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bool AltersExclusiveState() const;
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/// Determines whether or not this instruction causes a CPU exception.
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bool CausesCPUException() const;
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/// Determines whether or not this instruction may have side-effects.
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bool MayHaveSideEffects() const;
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size_t UseCount() const { return use_count; }
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bool HasUses() const { return use_count > 0; }
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void DecrementRemainingUses();
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/// Gets a pseudo-operation associated with this instruction.
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Inst* GetAssociatedPseudoOperation(Opcode opcode);
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/// Get the microop this microinstruction represents.
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Opcode GetOpcode() const { return op; }
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/// Get the type this instruction returns.
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Type GetType() const;
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/// Get the number of arguments this instruction has.
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size_t NumArgs() const { return GetNumArgsOf(op); }
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Value GetArg(size_t index) const;
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void SetArg(size_t index, Value value);
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void Invalidate();
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void ReplaceUsesWith(Value& replacement);
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private:
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void Use(Value& value);
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void UndoUse(Value& value);
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Opcode op;
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size_t use_count = 0;
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std::array<Value, 3> args;
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Inst* carry_inst = nullptr;
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Inst* overflow_inst = nullptr;
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};
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} // namespace IR
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} // namespace Dynarmic
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