Merge pull request #3 from FernandoS27/bit
Implemented the rest of the bitwise operations
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commit
bdf538bd64
2 changed files with 78 additions and 1 deletions
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@ -280,10 +280,30 @@ class Module {
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/// The least-significant bits will be zero filled.
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/// The least-significant bits will be zero filled.
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Id OpShiftLeftLogical(Id result_type, Id base, Id shift);
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Id OpShiftLeftLogical(Id result_type, Id base, Id shift);
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/// Does a bitwise Or between operands 1 and 2.
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Id OpBitwiseOr(Id result_type, Id operand_1, Id operand_2);
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/// Does a bitwise Xor between operands 1 and 2.
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Id OpBitwiseXor(Id result_type, Id operand_1, Id operand_2);
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/// Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
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/// Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
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/// Operand 1 or Operand 2 are 0.
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/// Operand 1 or Operand 2 are 0.
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Id OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2);
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Id OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2);
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/// Does a bitwise Not on the operand.
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Id OpNot(Id result_type, Id operand);
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Id OpBitFieldInsert(Id result_type, Id base, Id insert, Id offset,
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Id count);
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Id OpBitFieldSExtract(Id result_type, Id base, Id offset, Id count);
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Id OpBitFieldUExtract(Id result_type, Id base, Id offset, Id count);
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Id OpBitReverse(Id result_type, Id base);
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Id OpBitCount(Id result_type, Id base);
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// Arithmetic
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// Arithmetic
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/// Floating-point subtract of Operand from zero.
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/// Floating-point subtract of Operand from zero.
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@ -35,6 +35,20 @@ Id Module::OpShiftLeftLogical(Id result_type, Id base, Id shift) {
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return AddCode(std::move(op));
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return AddCode(std::move(op));
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}
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}
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Id Module::OpBitwiseOr(Id result_type, Id operand_1, Id operand_2) {
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auto op{std::make_unique<Op>(spv::Op::OpBitwiseOr, bound++, result_type)};
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op->Add(operand_1);
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op->Add(operand_2);
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return AddCode(std::move(op));
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}
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Id Module::OpBitwiseXor(Id result_type, Id operand_1, Id operand_2) {
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auto op{std::make_unique<Op>(spv::Op::OpBitwiseXor, bound++, result_type)};
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op->Add(operand_1);
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op->Add(operand_2);
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return AddCode(std::move(op));
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}
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Id Module::OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2) {
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Id Module::OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2) {
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auto op{std::make_unique<Op>(spv::Op::OpBitwiseAnd, bound++, result_type)};
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auto op{std::make_unique<Op>(spv::Op::OpBitwiseAnd, bound++, result_type)};
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op->Add(operand_1);
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op->Add(operand_1);
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@ -42,4 +56,47 @@ Id Module::OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2) {
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return AddCode(std::move(op));
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return AddCode(std::move(op));
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}
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}
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Id Module::OpNot(Id result_type, Id operand) {
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auto op{std::make_unique<Op>(spv::Op::OpNot, bound++, result_type)};
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op->Add(operand);
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return AddCode(std::move(op));
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}
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Id Module::OpBitFieldInsert(Id result_type, Id base, Id insert, Id offset, Id count) {
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auto op{std::make_unique<Op>(spv::Op::OpBitFieldInsert, bound++, result_type)};
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op->Add(base);
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op->Add(insert);
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op->Add(offset);
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op->Add(count);
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return AddCode(std::move(op));
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}
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Id Module::OpBitFieldSExtract(Id result_type, Id base, Id offset, Id count) {
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auto op{std::make_unique<Op>(spv::Op::OpBitFieldSExtract, bound++, result_type)};
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op->Add(base);
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op->Add(offset);
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op->Add(count);
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return AddCode(std::move(op));
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}
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Id Module::OpBitFieldUExtract(Id result_type, Id base, Id offset, Id count) {
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auto op{std::make_unique<Op>(spv::Op::OpBitFieldUExtract, bound++, result_type)};
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op->Add(base);
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op->Add(offset);
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op->Add(count);
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return AddCode(std::move(op));
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}
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Id Module::OpBitReverse(Id result_type, Id base) {
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auto op{std::make_unique<Op>(spv::Op::OpBitReverse, bound++, result_type)};
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op->Add(base);
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return AddCode(std::move(op));
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}
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Id Module::OpBitCount(Id result_type, Id base) {
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auto op{std::make_unique<Op>(spv::Op::OpBitCount, bound++, result_type)};
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op->Add(base);
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return AddCode(std::move(op));
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}
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} // namespace Sirit
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} // namespace Sirit
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