551 lines
14 KiB
Rust
551 lines
14 KiB
Rust
use std::io;
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use std::io::prelude::*;
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use std::fs::File;
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struct Cpu {
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memory: Vec<u8>,
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pc: u16,
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registers: Vec<u8>,
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i: u16,
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stack: Vec<u16>,
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sp: i8,
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dt: u8,
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st: u8,
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}
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impl Cpu {
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fn ramread(&self, index: usize) -> &u8 {
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&self.memory[index]
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}
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fn ramwrite(&mut self, index: usize, value: u8) {
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if index < 512 {
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println!("Segmentation fault in emulated CPU! Bailing out!");
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panic!()
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}
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self.memory[index] = value;
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}
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fn regread(&self, index: usize) -> &u8 {
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&self.registers[index]
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}
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fn regwrite(&mut self, index: usize, value: u8) {
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self.registers[index] = value;
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}
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fn iread(&self) -> &u16 {
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&self.i
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}
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fn iwrite(&mut self, value: u16) {
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self.i = value;
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}
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fn incrementpc(&mut self) {
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self.pc = self.pc + 2
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}
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fn fetch(&self) -> u16 {
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return ((self.memory[self.pc as usize] as u16) << 8 | self.memory[self.pc as usize + 1 as usize] as u16)
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}
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fn setpc(&mut self, prc: u16) {
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self.pc = prc;
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}
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fn incrementsp(&mut self) {
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self.sp = self.sp + 1
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}
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fn decrementsp(&mut self) {
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self.sp = self.sp - 1
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}
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fn stackpush(&mut self) {
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if self.stack.len() == 15 {
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println!("Stack overflow in emulated CPU! Bailing out!");
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panic!();
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}
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self.stack.push(self.pc);
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}
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fn stackpop(&mut self) -> u16 {
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if self.stack.len() == 0 {
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println!("Stack underflow in emulated CPU! Bailing out!");
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panic!();
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}
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let stacker = *self.stack.last().unwrap() as u16;
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self.stack.pop();
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return stacker;
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}
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}
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struct Instruction {
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name: &'static str,
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mask: u16,
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pattern: u16,
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masks: &'static [u16],
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shifts: &'static [u8],
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}
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const ISET: [Instruction; 34] = [Instruction { name: "CLS",
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mask: 0xffff,
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pattern: 0x00e0,
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masks: &[], shifts: &[] },
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Instruction { name: "RET",
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mask: 0xffff,
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pattern: 0x00ee,
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masks: &[], shifts: &[] },
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Instruction { name: "JP_ADDR",
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mask: 0xf000,
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pattern: 0x1000,
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masks: &[0x0fff], shifts: &[0] },
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Instruction { name: "CALL_ADDR",
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mask: 0xf000,
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pattern: 0x2000,
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masks: &[0x0fff], shifts: &[0] },
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Instruction { name: "SE_VX_BYTE",
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mask: 0xf000,
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pattern: 0x3000,
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masks: &[0x0f00, 0x00ff], shifts: &[8, 0] },
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Instruction { name: "SNE_VX_BYTE",
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mask: 0xf000,
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pattern: 0x4000,
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masks: &[0x0f00, 0x00ff], shifts: &[8, 0] },
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Instruction { name: "SE_VX_VY",
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mask: 0xf00f,
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pattern: 0x5000,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "LD_VX_BYTE",
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mask: 0xf000,
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pattern: 0x6000,
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masks: &[0x0f00, 0x00ff], shifts: &[8, 0] },
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Instruction { name: "ADD_VX_BYTE",
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mask: 0xf000,
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pattern: 0x7000,
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masks: &[0x0f00, 0x00ff], shifts: &[8, 0] },
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Instruction { name: "LD_VX_VY",
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mask: 0xf00f,
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pattern: 0x8000,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "OR_VX_VY",
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mask: 0xf00f,
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pattern: 0x8001,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "AND_VX_VY",
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mask: 0xf00f,
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pattern: 0x8002,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "XOR_VX_VY",
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mask: 0xf00f,
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pattern: 0x8003,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "ADD_VX_VY",
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mask: 0xf00f,
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pattern: 0x8004,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "SUB_VX_VY",
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mask: 0xf00f,
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pattern: 0x8005,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "SHR_VX_VY",
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mask: 0xf00f,
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pattern: 0x8006,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "SUBN_VX_VY",
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mask: 0xf00f,
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pattern: 0x8007,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "SHL_VX_VY",
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mask: 0xf00f,
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pattern: 0x800e,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "SNE_VX_VY",
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mask: 0xf00f,
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pattern: 0x9000,
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masks: &[0x0f00, 0x00f0], shifts: &[8, 4] },
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Instruction { name: "LD_I_ADDR",
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mask: 0xf000,
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pattern: 0xa000,
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masks: &[0x0fff], shifts: &[0] },
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Instruction { name: "JP_V0_ADDR",
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mask: 0xf000,
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pattern: 0xb000,
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masks: &[0x0fff], shifts: &[0] },
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Instruction { name: "RND_VX_BYTE",
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mask: 0xf000,
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pattern: 0xc000,
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masks: &[0x0f00, 0x00ff], shifts: &[8, 0] },
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Instruction { name: "DRW_VX_VY_NIBBLE",
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mask: 0xf000,
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pattern: 0xd000,
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masks: &[0x0f00, 0x00f0, 0x000f], shifts: &[8, 4, 0] },
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Instruction { name: "SKP_VX",
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mask: 0xf0ff,
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pattern: 0xe09e,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "SKNP_VX",
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mask: 0xf0ff,
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pattern: 0xe0a1,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_VX_DT",
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mask: 0xf0ff,
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pattern: 0xf007,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_VX_K",
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mask: 0xf0ff,
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pattern: 0xf00a,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_DT_VX",
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mask: 0xf0ff,
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pattern: 0xf015,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_ST_VX",
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mask: 0xf0ff,
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pattern: 0xf018,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "ADD_I_VX",
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mask: 0xf0ff,
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pattern: 0xf01e,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_F_VX",
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mask: 0xf0ff,
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pattern: 0xf029,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_B_VX",
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mask: 0xf0ff,
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pattern: 0xf033,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_IB_VX",
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mask: 0xf0ff,
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pattern: 0xf055,
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masks: &[0x0f00], shifts: &[8] },
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Instruction { name: "LD_VX_IB",
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mask: 0xf0ff,
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pattern: 0xf065,
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masks: &[0x0f00], shifts: &[8] }
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];
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fn disassemble(opcode: u16) -> Instruction {
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let mut instruction;
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for instr in ISET {
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if (opcode & instr.mask) == instr.pattern {
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instruction = instr;
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return instruction;
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}
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}
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println!("Invalid opcode 0x{}! Bailing out!", format!("{:x}", opcode));
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panic!();
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}
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fn decodetest(opcode: u16, expected: &str) {
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let instruction = disassemble(opcode);
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if instruction.name != expected {
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println!("Opcode 0x{} disassembled as instruction {}. Expected {}.", format!("{:x}", opcode), instruction.name, expected);
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}
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}
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fn execute(opcode: u16, instruction: Instruction, mut cpu: Cpu) -> Cpu {
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let mut args: Vec<u16> = vec![];
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let mut i = 0;
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if instruction.masks.len() != 0 {
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for mask in instruction.masks {
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let shift = instruction.shifts[i];
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args.push((opcode & mask) >> shift);
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i = i + 1;
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}
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}
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if instruction.name == "RET" {
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let returnaddress = cpu.stackpop();
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cpu.decrementsp();
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cpu.setpc(returnaddress);
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}
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else if instruction.name == "JP_ADDR" { cpu.setpc(args[0] as u16); }
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else if instruction.name == "CALL_ADDR" {
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cpu.incrementsp();
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cpu.stackpush();
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cpu.setpc(args[0] as u16);
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}
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else if instruction.name == "SE_VX_BYTE" {
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let register = args[0] as usize;
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let byte = args[1] as u8;
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if cpu.regread(register) == &byte {
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cpu.incrementpc();
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cpu.incrementpc();
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} else {
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cpu.incrementpc();
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}
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}
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else if instruction.name == "SNE_VX_BYTE" {
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let register = args[0] as usize;
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let byte = args[1] as u8;
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if cpu.regread(register) != &byte {
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cpu.incrementpc();
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cpu.incrementpc();
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} else {
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cpu.incrementpc();
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}
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}
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else if instruction.name == "SE_VX_VY" {
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let register1 = args[0] as usize;
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let register2 = args[1] as usize;
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if cpu.regread(register1) == cpu.regread(register2) {
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cpu.incrementpc();
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cpu.incrementpc();
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} else {
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cpu.incrementpc();
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}
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}
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else if instruction.name == "LD_VX_BYTE" {
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cpu.regwrite(args[0] as usize, args[1] as u8);
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cpu.incrementpc();
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}
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else if instruction.name == "ADD_VX_BYTE" {
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cpu.regwrite(args[0] as usize, (*cpu.regread(args[0] as usize) + args[1] as u8));
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cpu.incrementpc();
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}
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else if instruction.name == "LD_VX_VY" {
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cpu.regwrite(args[0] as usize, *cpu.regread(args[1] as usize));
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cpu.incrementpc();
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}
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else if instruction.name == "OR_VX_VY" {
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let result = *cpu.regread(args[0] as usize) | *cpu.regread(args[1] as usize);
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cpu.regwrite(args[0] as usize, result as u8);
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cpu.incrementpc();
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}
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else if instruction.name == "AND_VX_VY" {
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let result = *cpu.regread(args[0] as usize) & *cpu.regread(args[1] as usize);
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cpu.regwrite(args[0] as usize, result as u8);
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cpu.incrementpc();
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}
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else if instruction.name == "XOR_VX_VY" {
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let result = *cpu.regread(args[0] as usize) ^ *cpu.regread(args[1] as usize);
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cpu.regwrite(args[0] as usize, result as u8);
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cpu.incrementpc();
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}
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else if instruction.name == "ADD_VX_VY" {
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let reg1 = *cpu.regread(args[0] as usize) as u16;
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let reg2 = *cpu.regread(args[1] as usize) as u16;
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let bigresult = reg1 + reg2;
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if bigresult > 255 {
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// According to Cowgod, we can only keep the
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// lowest 8 bits and Rust does this fine when
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// you do bigresult as u8 so we are all good!
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cpu.regwrite(0xf as usize, 1 as u8);
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cpu.regwrite(args[0] as usize, bigresult as u8);
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} else {
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cpu.regwrite(0xf as usize, 0 as u8);
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cpu.regwrite(args[0] as usize, bigresult as u8);
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}
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cpu.incrementpc();
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}
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else if instruction.name == "SUB_VX_VY" {
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let reg1 = *cpu.regread(args[0] as usize) as u16;
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let reg2 = *cpu.regread(args[1] as usize) as u16;
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// Rust doesn't like it when you do arithmetic overflow so
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// I'm gonna fudge it :D
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if reg1 < reg2 {
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cpu.regwrite(args[0] as usize, 0);
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} else {
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if reg1 > reg2 {
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cpu.regwrite(0xf as usize, 1 as u8);
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} else {
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cpu.regwrite(0xf as usize, 0 as u8);
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}
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cpu.regwrite(args[0] as usize, (reg1 - reg2) as u8);
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}
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cpu.incrementpc();
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}
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else if instruction.name == "SHR_VX_VY" {
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let reg1 = *cpu.regread(args[0] as usize) as u16;
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if reg1 % 2 != 0 {
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cpu.regwrite(0xf as usize, 1 as u8);
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cpu.regwrite(args[0] as usize, ((reg1 - 2) / 2) as u8);
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} else {
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cpu.regwrite(0xf as usize, 0 as u8);
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cpu.regwrite(args[0] as usize, (reg1 / 2) as u8);
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}
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cpu.incrementpc();
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}
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else if instruction.name == "SUBN_VX_VY" {
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let reg1 = *cpu.regread(args[0] as usize) as u16;
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let reg2 = *cpu.regread(args[1] as usize) as u16;
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if reg1 > reg2 {
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cpu.regwrite(args[0] as usize, 0);
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} else {
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if reg1 < reg2 {
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cpu.regwrite(0xf as usize, 1 as u8);
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} else {
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cpu.regwrite(0xf as usize, 0 as u8);
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}
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cpu.regwrite(args[0] as usize, (reg2 - reg1) as u8);
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}
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cpu.incrementpc();
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}
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else if instruction.name == "SHL_VX_VY" {
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let reg1 = *cpu.regread(args[0] as usize) as u16;
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if reg1 % 2 != 0 {
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cpu.regwrite(0xf as usize, 1 as u8);
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cpu.regwrite(args[0] as usize, (reg1 * 2) as u8);
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} else {
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cpu.regwrite(0xf as usize, 0 as u8);
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cpu.regwrite(args[0] as usize, (reg1 * 2) as u8);
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}
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cpu.incrementpc();
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}
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else if instruction.name == "SNE_VX_VY" {
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let register1 = args[0] as usize;
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let register2 = args[1] as usize;
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if cpu.regread(register1) != cpu.regread(register2) {
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cpu.incrementpc();
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cpu.incrementpc();
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} else {
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cpu.incrementpc();
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}
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}
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else if instruction.name == "JP_V0_ADDR" { cpu.setpc(*cpu.regread(0) as u16 + args[0] as u16); }
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else if instruction.name == "LD_I_ADDR" {
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cpu.iwrite(args[0]);
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cpu.incrementpc();
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}
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else if instruction.name == "LD_VX_DT" {
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cpu.regwrite(args[0] as usize, cpu.dt);
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cpu.incrementpc();
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}
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else if instruction.name == "LD_DT_VX" {
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cpu.dt = *cpu.regread(args[0] as usize);
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cpu.incrementpc();
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}
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else if instruction.name == "LD_ST_VX" {
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cpu.st = *cpu.regread(args[0] as usize);
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cpu.incrementpc();
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}
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else if instruction.name == "ADD_I_VX" {
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cpu.iwrite(*cpu.iread() + (*cpu.regread(args[0] as usize)) as u16);
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cpu.incrementpc();
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}
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else if instruction.name == "LD_B_VX" {
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let i = *cpu.iread();
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let a = args[0] / 100;
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let b = (args[0] / 10) - (a * 10);
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let c = args[0] - (a * 100) - (b * 10);
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cpu.ramwrite(i as usize, a as u8);
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cpu.ramwrite(i as usize + 1 as usize, b as u8);
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cpu.ramwrite(i as usize + 2 as usize, c as u8);
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cpu.incrementpc();
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}
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else if instruction.name == "LD_IB_VX" {
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let i = *cpu.iread();
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let mut x = 0;
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let y = args[0];
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cpu.ramwrite(i as usize, *cpu.regread(0));
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while x != y {
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x = x + 1;
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cpu.ramwrite(i as usize + x as usize, *cpu.regread(x as usize));
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}
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cpu.incrementpc();
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}
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else if instruction.name == "LD_VX_IB" {
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let i = *cpu.iread();
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let mut x = 0;
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let y = args[0];
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cpu.regwrite(0, *cpu.ramread(i as usize));
|
|
|
|
while x != y {
|
|
x = x + 1;
|
|
cpu.regwrite(x as usize, *cpu.ramread(i as usize + x as usize));
|
|
}
|
|
|
|
cpu.incrementpc();
|
|
}
|
|
else {
|
|
println!("Unimplemented instruction {}. Skipping.", instruction.name);
|
|
cpu.incrementpc();
|
|
}
|
|
|
|
return cpu;
|
|
|
|
}
|
|
|
|
fn main() -> io::Result<()> {
|
|
let mut f = File::open("program.ch8")?;
|
|
let mut buffer: Vec<u8> = vec![];
|
|
println!("Buffer initialised!");
|
|
|
|
f.read_to_end(&mut buffer)?;
|
|
|
|
let mut cpu = Cpu { memory: vec![0; 4096], pc: 0x200, registers: vec![0; 16], i: 0, stack: vec![0; 16], sp: -1, dt: 0, st: 0 };
|
|
println!("CPU initialised!");
|
|
|
|
let mut i = 0x200;
|
|
|
|
for byte in buffer {
|
|
cpu.ramwrite(i, byte);
|
|
i = i + 1;
|
|
}
|
|
|
|
println!("File loaded to memory!");
|
|
|
|
torture();
|
|
println!("If you see messages above that are about opcodes, there's a bug!");
|
|
|
|
loop {
|
|
let mut opcode = cpu.fetch();
|
|
let mut instruction = disassemble(opcode);
|
|
cpu = execute(opcode, instruction, cpu);
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn torture() {
|
|
decodetest(0x00e0, "CLS");
|
|
decodetest(0x00ee, "RET");
|
|
decodetest(0x1123, "JP_ADDR");
|
|
decodetest(0x2123, "CALL_ADDR");
|
|
decodetest(0x3123, "SE_VX_BYTE");
|
|
decodetest(0x4123, "SNE_VX_BYTE");
|
|
decodetest(0x5120, "SE_VX_VY");
|
|
decodetest(0x6123, "LD_VX_BYTE");
|
|
decodetest(0x7123, "ADD_VX_BYTE");
|
|
decodetest(0x8120, "LD_VX_VY");
|
|
decodetest(0x8121, "OR_VX_VY");
|
|
decodetest(0x8122, "AND_VX_VY");
|
|
decodetest(0x8123, "XOR_VX_VY");
|
|
decodetest(0x8124, "ADD_VX_VY");
|
|
decodetest(0x8125, "SUB_VX_VY");
|
|
decodetest(0x8126, "SHR_VX_VY");
|
|
decodetest(0x8127, "SUBN_VX_VY");
|
|
decodetest(0x812e, "SHL_VX_VY");
|
|
decodetest(0x9120, "SNE_VX_VY");
|
|
decodetest(0xa123, "LD_I_ADDR");
|
|
decodetest(0xb123, "JP_V0_ADDR");
|
|
decodetest(0xc123, "RND_VX_BYTE");
|
|
decodetest(0xd123, "DRW_VX_VY_NIBBLE");
|
|
decodetest(0xe19e, "SKP_VX");
|
|
decodetest(0xe1a1, "SKNP_VX");
|
|
decodetest(0xf107, "LD_VX_DT");
|
|
decodetest(0xf10a, "LD_VX_K");
|
|
decodetest(0xf115, "LD_DT_VX");
|
|
decodetest(0xf118, "LD_ST_VX");
|
|
decodetest(0xf11e, "ADD_I_VX");
|
|
decodetest(0xf129, "LD_F_VX");
|
|
decodetest(0xf133, "LD_B_VX");
|
|
decodetest(0xf155, "LD_IB_VX");
|
|
decodetest(0xf165, "LD_VX_IB");
|
|
}
|