Add DEC instruction and fix JCZ, JCZR.
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13b3ec4b8d
commit
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1 changed files with 10 additions and 2 deletions
12
src/food8.rs
12
src/food8.rs
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@ -423,6 +423,14 @@ fn execute(opcode: u32, instruction: Instruction, mut cpu: Cpu) -> Cpu {
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cpu.regwrite(args[0] as usize, y+1);
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cpu.regwrite(args[0] as usize, y+1);
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}
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}
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cpu.incrementpc();
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cpu.incrementpc();
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} else if instruction.name == "DEC" {
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let y = cpu.regread(args[0] as usize).to_owned();
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if y == 0x00 {
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cpu.regwrite(args[0] as usize, 0xFF);
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} else {
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cpu.regwrite(args[0] as usize, y-1);
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}
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cpu.incrementpc();
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} else if instruction.name == "NOT" {
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} else if instruction.name == "NOT" {
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let y = cpu.regread(args[0] as usize).to_owned();
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let y = cpu.regread(args[0] as usize).to_owned();
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cpu.regwrite(args[0] as usize, !y);
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cpu.regwrite(args[0] as usize, !y);
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@ -463,7 +471,7 @@ fn execute(opcode: u32, instruction: Instruction, mut cpu: Cpu) -> Cpu {
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cpu.refreshcache();
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cpu.refreshcache();
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cpu.setpc(args[0] as u16);
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cpu.setpc(args[0] as u16);
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} else if instruction.name == "JCZ" {
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} else if instruction.name == "JCZ" {
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let y = cpu.regread(args[0] as usize);
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let y = cpu.regread(args[1] as usize);
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if *y == 0 {
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if *y == 0 {
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cpu.setpc(args[0] as u16);
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cpu.setpc(args[0] as u16);
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} else {
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} else {
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@ -471,7 +479,7 @@ fn execute(opcode: u32, instruction: Instruction, mut cpu: Cpu) -> Cpu {
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}
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}
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} else if instruction.name == "JCZR" {
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} else if instruction.name == "JCZR" {
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cpu.refreshcache();
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cpu.refreshcache();
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let y = cpu.regread(args[0] as usize);
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let y = cpu.regread(args[1] as usize);
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if *y == 0 {
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if *y == 0 {
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cpu.setpc(args[0] as u16);
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cpu.setpc(args[0] as u16);
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} else {
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} else {
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