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Field Of Operational Development 8-Bit Processor
(FOOD8)
instruction set
by threeoh6000
Published 15 May 2022
This document is licensed CC-BY-SA 4.0
Memory
----------
Memory in the FOOD8 allows for a maximum of 256 banks of 64 kilobytes.
Since execution of programs can span multiple banks, the processor has a 64K cache which is automatically updated to the next bank when the program reaches the end of the cache.
The current memory accessed can be independent to the cache memory but can be updated with an instruction and can be used to jump to a seperate known code point in a seperate bank of memory
Stack
---------
The stack pointer is capable of storing 4 memory addresses along with their bank. Upon a call to another memory bank, this results in the cache being updated while the old memory bank is stored in the stack so that upon a return exectuion can continue from where it left off.
This has the side effect of the return instruction forcing a refresh of the cache which could be problematic for polymorphic code.
Stack overflows or underflows should completely halt the CPU and, if applicable, dump the state and where the erroneous operation was performed.
Connectivity
----------------
Peripherals are accessed through the INP and OUT instructions and are therefore not mapped within memory.
There can be a maximum of 256 peripherals connected (00 to FF) with 00 being the null peripheral and not being remappable.
Physical or emulated coprocessors can also be connected as peripherals and can allow for bidirectional communication.
Instructions
----------------
The standard instruction length of FOOD8 is 32 bits (4 bytes), meaning one bank of memory can hold 16,384 instructions. Instructions can be shorter than 32 bits but must be padded with 0x00 to fit the correct length.
Memory isn't directly accessed by any instructions without a memory address.
Any instruction resulting in an overflow or underflow of registers should NOT halt zthe execution of the processor and should- wrap around.
Opcode, Assembly, Description
0x0n - Data
-----------
0x00, NOP, No Opcode
0x01 0xyyyy 0xzz, LOAD <y: memory addr> <z: register>, Load byte from memory into register.
0x02 0xyy 0xzzzz, STOR <y: register> <z: memory addr>, Store byte from register into memory
0x03 0xyy 0xzz, LOAD <y: register> <z: register>, Load byte from register y to register z.
0x04 0xyy 0xzz, STOR <y: byte> <z: register>, Store byte to register
0x05 0xyyyy 0xzz, SWAP <y: memory addr> <z: register>, Swap the values between memory address and register
0x06 0xyy 0xzz, SWAP <y: register> <z: register>, Swap register values
0x0c 0xyy 0xzz, INP <y: peripheral> <z: register>, store peripheral input to register
0x0d 0xyy 0xzz, OUT <y: register> <z: peripheral>, store register value in peripheral
0x0e 0xyy, BANK <y: memory bank>, Switches current memory to chosen bank
0x0f, REF, Refreshes the cache to the current selected memory bank, execution begins from the next memory address in that bank.
0x1n - Arithmetic
-----------------
0x10 0xyy 0xzz, ADD <y: register> <z: register>, Y = Y+Z
0x11 0xyy 0xzz, SUB <y: register> <z: register>, Y = Y-Z
0x12 0xyy 0xzz, MULT <y: register> <z: register>, Y = Y*Z
0x13 0xyy 0xzz, DIVD <y: register> <z: register>, Y = Y/Z
0x14 0xzz, INC <z: register>, Increment register by one.
0x15 0xzz, DEC <z: register>, Decrement register by one.
0x16 0xyy, NOT <y: register>, Perform a bitwise NOT
0x17 0xyy 0xzz, AND <y: register> <z: register>, Perform a bitwise AND
0x18 0xyy 0xzz, OR <y: register> <z: register>, Perform a bitwise OR
0x19 0xyy 0xzz, XOR <y: register> <z: register>, Perform a bitwise XOR
0x1a 0xyy 0xzz 0xaa, LESS <y: register> <z: register> <a: register>, Check if y is less than z and store the result in a
0x1b 0xyy 0xzz 0xaa, EQU <y: register> <z: register> <a: register>, CHeck if y and z are equal and store the result in a
0x2n - Flow Control
-------------------
0x20 0xyyyy, JMP <y: memory address>, Jump to specified memory address.
0x21 0xyyyy, JMR <y: memory address>, Refresh cache and jump to specified memory address.
0x22 0xyyyy 0xzz, JCZ <y: memory address> <z: register>, Jump to specified memory address if register is zero.
0x23 0xyyyy 0xzz, JCZR <y: memory address> <z: register>, Refresh cache and JCZ.
0x24 0xyyyy, CALL <y: memory address>, refresh cache and jump to memory location as well as pushing the location of where execution left off into the stack.
0x25, RET, Sets the bank and memory address to the top location on the stack, refreshes cache and jumps to that memory address.
0xFn - Miscellaneous
------------------------
0xFE, DUMP, Dumps the state of the processor and all of its registers and continues with execution. A processor crash is equivalent to a DUMP and HALT
0xFF, HALT, Immediately halts the CPU's execution