MerryMage
|
d5af052f06
|
A64: Implement CMGE (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9d85991906
|
A64: Implement CMHI, CMHS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
0df6725f73
|
A64: Implement SMAX, SMIN, UMAX, UMIN
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
adb7f5f86f
|
A64: Implement CMGT (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1f5b3bca43
|
Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8698f057d0
|
A64: Implement STXP, STLXP, LDXP, LDAXP
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2a6619d59c
|
A64: Implement CLREX
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b7a2c1a7df
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8756487554
|
A64: Partially implement MRS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd65bedfe
|
A64: Implement DSB, DMB
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
Lioncash
|
a9153218bd
|
A64: Implement NOT (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
aed4fd3ec3
|
A64: Implement FADD (vector), vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5f77ab28ee
|
A64: Implement SSHLL, SSHLL2
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3738043e58
|
A64: Implement DUP (element), vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ce7628b6b5
|
load_store_multiple_structures: Improve IR codegen for selem == 1 case
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f1cb5581c9
|
A64: Implement FSUB (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c9b4f0114
|
A64: Implement CNT
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1dd2b33b87
|
A64: Implement MLS (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5eac3abf52
|
A64: Implement MLA (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3afd2fcbad
|
A64: Implement MUL (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e7041d7196
|
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a455ff70c9
|
decoder/a64: Don't rearrange unrelated decoders
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
faeb77e8c4
|
A64: Implement SUB (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bd106c3ae7
|
A64: Implement SIMD instruction SSRA, vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f58aba9871
|
A64: Implement SIMD instruction SSHR, vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
653c82d8f0
|
impl: Improve Vpart setter
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
3f93c77ace
|
A64: Implement SIMD instruction USRA, vector variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
fb9d20f27f
|
A64: Implement SIMD instruction USHR, vector variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7ff280827b
|
A64: Implement SIMD instructions USHLL, USHLL2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d3a4e1efe2
|
IR: Vector instructions now take esize argument in emitter
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
15e8231f24
|
opcodes: Sort vector IR opcodes alphabetically
|
2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
15871910af
|
Implemented BSL, BIC, BIT and BIF vector instructions
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
4e33629b0e
|
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
35a29a9665
|
A64: Implement ZIP1
|
2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
586854117b
|
Implemented UMULH and SMULH instructions
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1a7b7b541a
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8ab7d8175c
|
impl: Add AdvSIMDExpandImm
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ea69cb4474
|
A64: Implement SUB (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
|
A64: Implement ADD (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2a0850c068
|
A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7b33772ac6
|
A64: Implement BIC (vector, register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
eb5591859c
|
A64: Implement FMOV (general)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
dd88cee15a
|
translate/impl: Add Vpart
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
cc9efd13c9
|
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
81713c2b77
|
A64: Implement FCCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
aac5af50e2
|
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
2ee39d6b36
|
A64: Implement FMOV (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b02b861242
|
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
5a65313236
|
A64: Implement CCMP (immediate)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab4664de61
|
A64: Implement CCMN (immediate)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a6c6539109
|
A64: Implement CCMP (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
c5033b5dda
|
A64: Implement CCMN (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4491746eae
|
A64: Implement FNEG
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
db958061a3
|
A64: Implement FABS
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8765b421b7
|
A64: Implement FCSEL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7e82d8eede
|
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2409e5d082
|
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
56bc7825ef
|
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
40614202e7
|
A64: Implement AESD
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ccef85dbb7
|
A64: Implement AESE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
0bb4474fb9
|
A64: Implement INS (general)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d13704fdef
|
A64: Implement INS (element)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
0642d49919
|
A64: Implement SMOV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
5297027ebe
|
A64: Implement UMOV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1fb0957aa3
|
A64: Implement FCVT
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4be55b8b84
|
A64: Implement FMOV (scalar, immediate)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
a07c05ea51
|
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
93fcbdf1e2
|
A64: Implement FCMP, FCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
99d8ebe4d5
|
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ed2bedec43
|
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
af1384d700
|
A64: Implement CRC32
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
d7044bc751
|
assert: Use fmt in ASSERT_MSG
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
52268298a8
|
a64_emit_x64: Perform RSB predictions
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7734cf1050
|
A64: Implement EXTR
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
88ae7fce52
|
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
b513b2ef05
|
IR: Implement IR instructions A64{Get,Set}S
|
2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
|
2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
7abd673a49
|
A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
ba3d6da0c8
|
load_store_register_unprivileged: bug: LDTRSW
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
75756137c6
|
A64: Implement CMEQ (register, vector)
|
2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
|
e0c12ec2ad
|
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
589ad7232f
|
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
ae880d8391
|
A64: Fix bugs and address review comments
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
3aeb7ca50c
|
Add missing returns
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
41e6e659c5
|
A64: Implement Load/Store register (unprivileged)
|
2020-04-22 20:44:37 +01:00 |
|
FernandoS27
|
ab84524806
|
Implemented SDIV and UDIV instructions
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
6033b05ca6
|
A64: Implement LDR/STR (immediate, SIMD&FP)
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
e1df7ae621
|
IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
3caf192f60
|
A64: Implement DUP (general)
|
2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
6f9216d544
|
A64: Implement RBIT
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
d4b05b28cf
|
A64: Implement CLS
This is not the cleanest implementation.
|
2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
b8e26bfdc3
|
A64: Implement ADDP (vector)
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
bb1c5bd3b2
|
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
|
2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
c1a25bfc2f
|
A64: Implement MADD and MSUB
|
2020-04-22 20:42:46 +01:00 |
|