Lioncash
b7c5055d42
A64: Implement CLZ
2020-04-22 20:42:46 +01:00
MerryMage
4c4efb2213
data_processing_register: Clean-up
2020-04-22 20:42:46 +01:00
Lioncash
ae5dbcbed6
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
...
Truly the most difficult A64 instructions to implement.
2020-04-22 20:42:46 +01:00
Lioncash
4d8f4aa8af
A64: Implement ASRV, LSLV, LSRV, and RORV
2020-04-22 20:42:46 +01:00
Lioncash
a8a65beb2b
data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG
2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536
A64: Implement AND (vector)
2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
Thomas Guillemard
896cf44f96
A64: Implement REV, REV32, and REV16 ( #126 )
2020-04-22 20:42:46 +01:00
MerryMage
144b629d8a
A64: Implement CSEL
2020-04-22 20:42:45 +01:00
MerryMage
19da68568e
A64/translate/branch: bug: Read-after-write error in BLR
2020-04-22 20:42:45 +01:00
MerryMage
9f57283a30
A64: Implement SBFM, BFM, UBFM
2020-04-22 20:42:45 +01:00
MerryMage
cdbc8d07a5
A64: Implement MOVN, MOVZ, MOVK
2020-04-22 20:42:45 +01:00
MerryMage
21fe61eac6
A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
2020-04-22 20:42:45 +01:00
MerryMage
7c4b70751c
A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
2020-04-22 20:42:45 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
61125d6dd1
A64/translate: Add TranslateSingleInstruction function
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
595f157e5e
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
243f06c613
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
25411da838
A32: Implement load stores (immediate)
2020-04-22 20:42:45 +01:00
MerryMage
2aadeec291
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48
A64: Implement compare and branch
2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3
A64: Implement branch (register)
2020-04-22 20:42:45 +01:00
MerryMage
86d1095df7
A64: Implement branch
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
5a1d88c5dc
A64: Implement pcrel
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93
A64: Backend framework
2020-04-22 20:42:44 +01:00
MerryMage
e161cf16f5
A64: Initial framework
2020-04-22 20:42:44 +01:00
