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dynarmic/src/frontend/ir/opcodes.inc

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First Commit
2016-07-01 14:01:06 +01:00
// opcode name, return type, arg1 type, arg2 type, arg3 type, ...
ir_opt: Remove redundant shift instructions
2017-02-18 21:46:36 +00:00
OPCODE(Void, T::Void, )
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
OPCODE(Identity, T::Opaque, T::Opaque )
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
2016-08-05 14:07:27 +01:00
OPCODE(Breakpoint, T::Void, )
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
// A32 Context getters/setters
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2018-01-05 20:30:41 +00:00
A32OPC(GetRegister, T::U32, T::A32Reg )
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.
2018-01-19 01:09:46 +00:00
A32OPC(GetExtendedRegister32, T::U32, T::A32ExtReg )
A32OPC(GetExtendedRegister64, T::U64, T::A32ExtReg )
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2018-01-05 20:30:41 +00:00
A32OPC(SetRegister, T::Void, T::A32Reg, T::U32 )
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.
2018-01-19 01:09:46 +00:00
A32OPC(SetExtendedRegister32, T::Void, T::A32ExtReg, T::U32 )
A32OPC(SetExtendedRegister64, T::Void, T::A32ExtReg, T::U64 )
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
A32OPC(GetCpsr, T::U32, )
A32OPC(SetCpsr, T::Void, T::U32 )
A32OPC(SetCpsrNZCV, T::Void, T::U32 )
A32OPC(SetCpsrNZCVQ, T::Void, T::U32 )
A32OPC(GetNFlag, T::U1, )
A32OPC(SetNFlag, T::Void, T::U1 )
A32OPC(GetZFlag, T::U1, )
A32OPC(SetZFlag, T::Void, T::U1 )
A32OPC(GetCFlag, T::U1, )
A32OPC(SetCFlag, T::Void, T::U1 )
A32OPC(GetVFlag, T::U1, )
A32OPC(SetVFlag, T::Void, T::U1 )
A32OPC(OrQFlag, T::Void, T::U1 )
A32OPC(GetGEFlags, T::U32, )
A32OPC(SetGEFlags, T::Void, T::U32 )
A32OPC(SetGEFlagsCompressed, T::Void, T::U32 )
A32OPC(BXWritePC, T::Void, T::U32 )
A32OPC(CallSupervisor, T::Void, T::U32 )
A32: Add ExceptionRaised IR instruction and use it
2018-01-28 12:55:47 +00:00
A32OPC(ExceptionRaised, T::Void, T::U32, T::U64 )
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
A32OPC(GetFpscr, T::U32, )
A32OPC(SetFpscr, T::Void, T::U32, )
A32OPC(GetFpscrNZCV, T::U32, )
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2018-02-05 12:16:01 +00:00
A32OPC(SetFpscrNZCV, T::Void, T::NZCVFlags )
First Commit
2016-07-01 14:01:06 +01:00
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
// A64 Context getters/setters
A64: Implement compare and branch
2018-01-07 16:33:02 +00:00
A64OPC(SetCheckBit, T::Void, T::U1 )
A64: Implement addsub instructions
2018-01-07 11:31:20 +00:00
A64OPC(GetCFlag, T::U1, )
A64OPC(SetNZCV, T::Void, T::NZCVFlags )
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
A64OPC(GetW, T::U32, T::A64Reg )
A64OPC(GetX, T::U64, T::A64Reg )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
//A64OPC(GetB, T::U128, T::A64Vec )
//A64OPC(GetH, T::U128, T::A64Vec )
IR: Implement IR instructions A64{Get,Set}S
2018-01-26 18:35:19 +00:00
A64OPC(GetS, T::U128, T::A64Vec )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
A64OPC(GetD, T::U128, T::A64Vec )
A64OPC(GetQ, T::U128, T::A64Vec )
A64: Implement addsub instructions
2018-01-07 11:31:20 +00:00
A64OPC(GetSP, T::U64, )
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
A64OPC(SetW, T::Void, T::A64Reg, T::U32 )
A64OPC(SetX, T::Void, T::A64Reg, T::U64 )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
//A64OPC(SetB, T::Void, T::A64Vec, T::U8 )
//A64OPC(SetH, T::Void, T::A64Vec, T::U16 )
IR: Implement IR instructions A64{Get,Set}S
2018-01-26 18:35:19 +00:00
A64OPC(SetS, T::Void, T::A64Vec, T::U128 )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
A64OPC(SetD, T::Void, T::A64Vec, T::U128 )
A64OPC(SetQ, T::Void, T::A64Vec, T::U128 )
A64: Implement addsub instructions
2018-01-07 11:31:20 +00:00
A64OPC(SetSP, T::Void, T::U64 )
A64: Implement branch (register)
2018-01-07 13:56:32 +00:00
A64OPC(SetPC, T::Void, T::U64 )
A64: Implement SVC
2018-01-08 22:03:03 +00:00
A64OPC(CallSupervisor, T::Void, T::U32 )
A64: Add ExceptionRaised IR instruction The purpose of this instruction is to raise exceptions when certain decode-time issues happen, instead of asserting at translate time. This allows us to use the translator for code analysis without worrying about unnecessary asserts, but also provides flexibility for the library user to perform custom behaviour when one of these states are raised.
2018-01-13 17:54:29 +00:00
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
// Hints
OPCODE(PushRSB, T::Void, T::U64 )
First Commit
2016-07-01 14:01:06 +01:00
// Pseudo-operation, handled specially at final emit
OPCODE(GetCarryFromOp, T::U1, T::U32 )
Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
2016-07-08 10:09:18 +01:00
OPCODE(GetOverflowFromOp, T::U1, T::U32 )
IR: Implement new pseudo-operation GetGEFromOp
2016-12-04 20:52:06 +00:00
OPCODE(GetGEFromOp, T::U32, T::U32 )
A64: Implement addsub instructions
2018-01-07 11:31:20 +00:00
OPCODE(GetNZCVFromOp, T::NZCVFlags, T::Opaque )
First Commit
2016-07-01 14:01:06 +01:00
IR: Add IR instruction NZCVFromPackedFlags This instruction expects NZCV to be in the high bits. i.e.: The positions they were in PSTATE.
2018-02-03 13:34:40 +00:00
OPCODE(NZCVFromPackedFlags, T::NZCVFlags, T::U32 )
First Commit
2016-07-01 14:01:06 +01:00
// Calculations
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(Pack2x32To1x64, T::U64, T::U32, T::U32 )
OPCODE(LeastSignificantWord, T::U32, T::U64 )
OPCODE(MostSignificantWord, T::U32, T::U64 )
Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
2016-07-11 23:06:35 +01:00
OPCODE(LeastSignificantHalf, T::U16, T::U32 )
First Commit
2016-07-01 14:01:06 +01:00
OPCODE(LeastSignificantByte, T::U8, T::U32 )
OPCODE(MostSignificantBit, T::U1, T::U32 )
A64: Implement compare and branch
2018-01-07 16:33:02 +00:00
OPCODE(IsZero32, T::U1, T::U32 )
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(IsZero64, T::U1, T::U64 )
A64: Implement compare and branch
2018-01-07 16:33:02 +00:00
OPCODE(TestBit, T::U1, T::U64, T::U8 )
IR: Implement Conditional Select
2018-01-18 11:36:48 +00:00
OPCODE(ConditionalSelect32, T::U32, T::Cond, T::U32, T::U32 )
OPCODE(ConditionalSelect64, T::U64, T::Cond, T::U64, T::U64 )
IR: Add ConditionalSelectNZCV instruction
2018-02-04 23:07:51 +00:00
OPCODE(ConditionalSelectNZCV, T::NZCVFlags, T::Cond, T::NZCVFlags, T::NZCVFlags )
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
OPCODE(LogicalShiftLeft32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftLeft64, T::U64, T::U64, T::U8 )
OPCODE(LogicalShiftRight32, T::U32, T::U32, T::U8, T::U1 )
Add simplified LogicalShiftRight64 IR opcode
2016-08-07 14:23:33 +01:00
OPCODE(LogicalShiftRight64, T::U64, T::U64, T::U8 )
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
OPCODE(ArithmeticShiftRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(ArithmeticShiftRight64, T::U64, T::U64, T::U8 )
OPCODE(RotateRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(RotateRight64, T::U64, T::U64, T::U8 )
Add IR opcode RotateRightExtended to rotate through the carry flag
2016-07-31 19:07:35 +01:00
OPCODE(RotateRightExtended, T::U32, T::U32, T::U1 )
A64: Implement addsub instructions
2018-01-07 11:31:20 +00:00
OPCODE(Add32, T::U32, T::U32, T::U32, T::U1 )
OPCODE(Add64, T::U64, T::U64, T::U64, T::U1 )
OPCODE(Sub32, T::U32, T::U32, T::U32, T::U1 )
OPCODE(Sub64, T::U64, T::U64, T::U64, T::U1 )
OPCODE(Mul32, T::U32, T::U32, T::U32 )
Add more IR opcodes for multiply instructions Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-04 22:04:42 +01:00
OPCODE(Mul64, T::U64, T::U64, T::U64 )
Implemented UMULH and SMULH instructions
2018-01-27 16:32:07 +00:00
OPCODE(SignedMultiplyHigh64, T::U64, T::U64, T::U64 )
OPCODE(UnsignedMultiplyHigh64, T::U64, T::U64, T::U64 )
Implemented SDIV and UDIV instructions
2018-01-24 12:36:39 +00:00
OPCODE(UnsignedDiv32, T::U32, T::U32, T::U32 )
OPCODE(UnsignedDiv64, T::U64, T::U64, T::U64 )
OPCODE(SignedDiv32, T::U32, T::U32, T::U32 )
OPCODE(SignedDiv64, T::U64, T::U64, T::U64 )
A64: Implement logical
2018-01-07 12:52:12 +00:00
OPCODE(And32, T::U32, T::U32, T::U32 )
OPCODE(And64, T::U64, T::U64, T::U64 )
OPCODE(Eor32, T::U32, T::U32, T::U32 )
OPCODE(Eor64, T::U64, T::U64, T::U64 )
OPCODE(Or32, T::U32, T::U32, T::U32 )
OPCODE(Or64, T::U64, T::U64, T::U64 )
OPCODE(Not32, T::U32, T::U32 )
OPCODE(Not64, T::U64, T::U64 )
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +01:00
OPCODE(SignExtendByteToWord, T::U32, T::U8 )
A64: Implement addsub instructions
2018-01-07 11:31:20 +00:00
OPCODE(SignExtendHalfToWord, T::U32, T::U16 )
OPCODE(SignExtendByteToLong, T::U64, T::U8 )
OPCODE(SignExtendHalfToLong, T::U64, T::U16 )
OPCODE(SignExtendWordToLong, T::U64, T::U32 )
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +01:00
OPCODE(ZeroExtendByteToWord, T::U32, T::U8 )
A64: Implement addsub instructions
2018-01-07 11:31:20 +00:00
OPCODE(ZeroExtendHalfToWord, T::U32, T::U16 )
OPCODE(ZeroExtendByteToLong, T::U64, T::U8 )
OPCODE(ZeroExtendHalfToLong, T::U64, T::U16 )
OPCODE(ZeroExtendWordToLong, T::U64, T::U32 )
IR: Add IR instruction ZeroExtendToQuad
2018-01-24 15:54:11 +00:00
OPCODE(ZeroExtendLongToQuad, T::U128, T::U64 )
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +01:00
OPCODE(ByteReverseWord, T::U32, T::U32 )
OPCODE(ByteReverseHalf, T::U16, T::U16 )
Implement memory endianness. Implement Thumb SETEND instruction.
2016-07-20 15:34:17 +01:00
OPCODE(ByteReverseDual, T::U64, T::U64 )
opcodes: Add 64-bit CountLeadingZeroes opcode
2018-01-22 15:51:40 +00:00
OPCODE(CountLeadingZeros32, T::U32, T::U32 )
OPCODE(CountLeadingZeros64, T::U64, T::U64 )
A64: Implement EXTR
2018-01-26 16:49:08 +00:00
OPCODE(ExtractRegister32, T::U32, T::U32, T::U32, T::U8 )
OPCODE(ExtractRegister64, T::U64, T::U64, T::U64, T::U8 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
// Saturated instructions
OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )
OPCODE(SignedSaturatedSub, T::U32, T::U32, T::U32 )
IR: Add microinstructions UnsignedSaturation and SignedSaturation
2016-12-21 14:16:48 +00:00
OPCODE(UnsignedSaturation, T::U32, T::U32, T::U8 )
OPCODE(SignedSaturation, T::U32, T::U32, T::U8 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
// Packed instructions
Implement UADD8
2016-12-04 20:52:33 +00:00
OPCODE(PackedAddU8, T::U32, T::U32, T::U32 )
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-18 16:25:41 +00:00
OPCODE(PackedAddS8, T::U32, T::U32, T::U32 )
Implement USUB8
2016-12-05 00:27:59 +00:00
OPCODE(PackedSubU8, T::U32, T::U32, T::U32 )
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-18 16:25:41 +00:00
OPCODE(PackedSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubS16, T::U32, T::U32, T::U32 )
parallel: Add and Subtract with Exchange improvements * Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction * Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions * Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
OPCODE(PackedAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddS16, T::U32, T::U32, T::U32 )
Implemented the ARM UHADD8 instruction. (#45) The x64 implementation uses the SSSE3 instruction PSHUFB. A non-SSE fallback is provided in case the CPU doesn't support it.
2016-11-25 20:32:22 +00:00
OPCODE(PackedHalvingAddU8, T::U32, T::U32, T::U32 )
Implement SHADD8 and SHADD16 (#47)
2016-11-26 18:12:29 +00:00
OPCODE(PackedHalvingAddS8, T::U32, T::U32, T::U32 )
Implement UHSUB8 and UHSUB16 (#48)
2016-11-26 18:27:21 +00:00
OPCODE(PackedHalvingSubU8, T::U32, T::U32, T::U32 )
Implement SHSUB8 and SHSUB16 (#74) * Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
OPCODE(PackedHalvingSubS8, T::U32, T::U32, T::U32 )
Implemented UHADD16
2016-11-26 11:28:20 +00:00
OPCODE(PackedHalvingAddU16, T::U32, T::U32, T::U32 )
Implement SHADD8 and SHADD16 (#47)
2016-11-26 18:12:29 +00:00
OPCODE(PackedHalvingAddS16, T::U32, T::U32, T::U32 )
Implement UHSUB8 and UHSUB16 (#48)
2016-11-26 18:27:21 +00:00
OPCODE(PackedHalvingSubU16, T::U32, T::U32, T::U32 )
Implement SHSUB8 and SHSUB16 (#74) * Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
OPCODE(PackedHalvingSubS16, T::U32, T::U32, T::U32 )
parallel: Add and Subtract with Exchange improvements * Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction * Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions * Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
OPCODE(PackedHalvingAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddS16, T::U32, T::U32, T::U32 )
TranslateArm: Implement QADD8 and UQADD8.
2016-08-12 18:26:14 +01:00
OPCODE(PackedSaturatedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS8, T::U32, T::U32, T::U32 )
TranslateArm: Implement UQSUB8.
2016-08-12 16:53:16 +01:00
OPCODE(PackedSaturatedSubU8, T::U32, T::U32, T::U32 )
TranslateArm: Implement QSUB8.
2016-08-12 18:18:38 +01:00
OPCODE(PackedSaturatedSubS8, T::U32, T::U32, T::U32 )
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
2016-08-12 18:42:16 +01:00
OPCODE(PackedSaturatedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS16, T::U32, T::U32, T::U32 )
Implemented USAD8 and USADA8
2016-12-17 19:52:22 +00:00
OPCODE(PackedAbsDiffSumS8, T::U32, T::U32, T::U32 )
Implement IR instruction PackedSelect, reimplement SEL
2017-11-25 16:33:48 +00:00
OPCODE(PackedSelect, T::U32, T::U32, T::U32, T::U32 )
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +01:00
A64: Implement CRC32C
2018-01-25 17:51:45 +00:00
// CRC instructions
OPCODE(CRC32Castagnoli8, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli16, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli32, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli64, T::U32, T::U32, T::U64 )
A64: Implement CRC32
2018-01-28 06:41:58 +00:00
OPCODE(CRC32ISO8, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO16, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO32, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO64, T::U32, T::U32, T::U64 )
A64: Implement CRC32C
2018-01-25 17:51:45 +00:00
A64: Implement AESIMC and AESMC
2018-01-30 12:56:18 +00:00
// AES instructions
A64: Implement AESD
2018-02-03 22:20:21 +00:00
OPCODE(AESDecryptSingleRound, T::U128, T::U128 )
OPCODE(AESEncryptSingleRound, T::U128, T::U128 )
A64: Implement AESIMC and AESMC
2018-01-30 12:56:18 +00:00
OPCODE(AESInverseMixColumns, T::U128, T::U128 )
OPCODE(AESMixColumns, T::U128, T::U128 )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
// Vector instructions
IR: Add IR instruction VectorGetElement{8,16,32,64}
2018-01-24 15:54:56 +00:00
OPCODE(VectorGetElement8, T::U8, T::U128, T::U8 )
OPCODE(VectorGetElement16, T::U16, T::U128, T::U8 )
OPCODE(VectorGetElement32, T::U32, T::U128, T::U8 )
OPCODE(VectorGetElement64, T::U64, T::U128, T::U8 )
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2018-02-02 21:07:51 +00:00
OPCODE(VectorSetElement8, T::U128, T::U128, T::U8, T::U8 )
OPCODE(VectorSetElement16, T::U128, T::U128, T::U8, T::U16 )
OPCODE(VectorSetElement32, T::U128, T::U128, T::U8, T::U32 )
OPCODE(VectorSetElement64, T::U128, T::U128, T::U8, T::U64 )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
OPCODE(VectorAdd8, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd64, T::U128, T::U128, T::U128 )
A64: Implement AND (vector)
2018-01-21 18:27:06 +00:00
OPCODE(VectorAnd, T::U128, T::U128, T::U128 )
opcodes: Sort vector IR opcodes alphabetically
2018-02-10 09:15:01 +00:00
OPCODE(VectorBroadcastLower8, T::U128, T::U8 )
OPCODE(VectorBroadcastLower16, T::U128, T::U16 )
OPCODE(VectorBroadcastLower32, T::U128, T::U32 )
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
2018-01-24 12:00:28 +00:00
OPCODE(VectorBroadcast8, T::U128, T::U8 )
OPCODE(VectorBroadcast16, T::U128, T::U16 )
OPCODE(VectorBroadcast32, T::U128, T::U32 )
OPCODE(VectorBroadcast64, T::U128, T::U64 )
opcodes: Sort vector IR opcodes alphabetically
2018-02-10 09:15:01 +00:00
OPCODE(VectorEor, T::U128, T::U128, T::U128 )
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
2018-01-26 01:52:06 +00:00
OPCODE(VectorEqual8, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual16, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual32, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual64, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual128, T::U128, T::U128, T::U128 )
A64: Implement ZIP1
2018-02-05 03:29:14 +00:00
OPCODE(VectorInterleaveLower8, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower16, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower32, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower64, T::U128, T::U128, T::U128 )
opcodes: Sort vector IR opcodes alphabetically
2018-02-10 09:15:01 +00:00
OPCODE(VectorNot, T::U128, T::U128 )
OPCODE(VectorOr, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower8, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower16, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower32, T::U128, T::U128, T::U128 )
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
2018-01-23 16:45:28 +00:00
OPCODE(VectorPairedAdd8, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
IR: Add IR instruction VectorZeroUpper
2018-01-24 17:11:13 +00:00
OPCODE(VectorZeroUpper, T::U128, T::U128 )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point operations
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.
2018-01-19 01:09:46 +00:00
OPCODE(FPAbs32, T::U32, T::U32 )
OPCODE(FPAbs64, T::U64, T::U64 )
OPCODE(FPAdd32, T::U32, T::U32, T::U32 )
OPCODE(FPAdd64, T::U64, T::U64, T::U64 )
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2018-02-05 12:16:01 +00:00
OPCODE(FPCompare32, T::NZCVFlags, T::U32, T::U32, T::U1 )
OPCODE(FPCompare64, T::NZCVFlags, T::U64, T::U64, T::U1 )
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.
2018-01-19 01:09:46 +00:00
OPCODE(FPDiv32, T::U32, T::U32, T::U32 )
OPCODE(FPDiv64, T::U64, T::U64, T::U64 )
OPCODE(FPMul32, T::U32, T::U32, T::U32 )
OPCODE(FPMul64, T::U64, T::U64, T::U64 )
OPCODE(FPNeg32, T::U32, T::U32 )
OPCODE(FPNeg64, T::U64, T::U64 )
OPCODE(FPSqrt32, T::U32, T::U32 )
OPCODE(FPSqrt64, T::U64, T::U64 )
OPCODE(FPSub32, T::U32, T::U32, T::U32 )
OPCODE(FPSub64, T::U64, T::U64, T::U64 )
VFP: Implement VADD.{F32,F64}
2016-08-06 17:21:29 +01:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point conversions
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.
2018-01-19 01:09:46 +00:00
OPCODE(FPSingleToDouble, T::U64, T::U32 )
OPCODE(FPDoubleToSingle, T::U32, T::U64 )
OPCODE(FPSingleToU32, T::U32, T::U32, T::U1 )
OPCODE(FPSingleToS32, T::U32, T::U32, T::U1 )
OPCODE(FPDoubleToU32, T::U32, T::U64, T::U1 )
OPCODE(FPDoubleToS32, T::U32, T::U64, T::U1 )
OPCODE(FPU32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPS32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPU32ToDouble, T::U64, T::U32, T::U1 )
OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 )
Implement VCVT
2016-08-23 22:04:46 +01:00
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
// A32 Memory access
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
A32OPC(ClearExclusive, T::Void, )
A32OPC(SetExclusive, T::Void, T::U32, T::U8 )
A32OPC(ReadMemory8, T::U8, T::U32 )
A32OPC(ReadMemory16, T::U16, T::U32 )
A32OPC(ReadMemory32, T::U32, T::U32 )
A32OPC(ReadMemory64, T::U64, T::U32 )
A32OPC(WriteMemory8, T::Void, T::U32, T::U8 )
A32OPC(WriteMemory16, T::Void, T::U32, T::U16 )
A32OPC(WriteMemory32, T::Void, T::U32, T::U32 )
A32OPC(WriteMemory64, T::Void, T::U32, T::U64 )
A32OPC(ExclusiveWriteMemory8, T::U32, T::U32, T::U8 )
A32OPC(ExclusiveWriteMemory16, T::U32, T::U32, T::U16 )
A32OPC(ExclusiveWriteMemory32, T::U32, T::U32, T::U32 )
A32OPC(ExclusiveWriteMemory64, T::U32, T::U32, T::U32, T::U32 )
Implement coprocessor-related microinstructions * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords
2016-12-31 11:17:47 +00:00
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
// A64 Memory access
A64OPC(ReadMemory8, T::U8, T::U64 )
A64OPC(ReadMemory16, T::U16, T::U64 )
A64OPC(ReadMemory32, T::U32, T::U64 )
A64OPC(ReadMemory64, T::U64, T::U64 )
IR: Add IR instructions A64Memory{Read,Write}128 This implementation only works on macOS and Linux.
2018-01-24 15:55:59 +00:00
A64OPC(ReadMemory128, T::U128, T::U64 )
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
A64OPC(WriteMemory8, T::Void, T::U64, T::U8 )
A64OPC(WriteMemory16, T::Void, T::U64, T::U16 )
A64OPC(WriteMemory32, T::Void, T::U64, T::U32 )
A64OPC(WriteMemory64, T::Void, T::U64, T::U64 )
IR: Add IR instructions A64Memory{Read,Write}128 This implementation only works on macOS and Linux.
2018-01-24 15:55:59 +00:00
A64OPC(WriteMemory128, T::Void, T::U64, T::U128 )
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
Implement coprocessor-related microinstructions * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords
2016-12-31 11:17:47 +00:00
// Coprocessor
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
A32OPC(CoprocInternalOperation, T::Void, T::CoprocInfo )
A32OPC(CoprocSendOneWord, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocSendTwoWords, T::Void, T::CoprocInfo, T::U32, T::U32 )
A32OPC(CoprocGetOneWord, T::U32, T::CoprocInfo )
A32OPC(CoprocGetTwoWords, T::U64, T::CoprocInfo )
A32OPC(CoprocLoadWords, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocStoreWords, T::Void, T::CoprocInfo, T::U32 )
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