2018-01-06 21:15:25 +00:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include <initializer_list>
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2018-02-11 22:53:46 +00:00
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#include <boost/optional.hpp>
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2018-01-13 17:54:29 +00:00
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#include <dynarmic/A64/config.h>
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2018-01-06 21:15:25 +00:00
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#include "common/common_types.h"
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#include "frontend/A64/location_descriptor.h"
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#include "frontend/A64/types.h"
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#include "frontend/ir/ir_emitter.h"
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#include "frontend/ir/value.h"
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2018-01-26 13:51:48 +00:00
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namespace Dynarmic::A64 {
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2018-01-06 21:15:25 +00:00
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/**
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* Convenience class to construct a basic block of the intermediate representation.
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* `block` is the resulting block.
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* The user of this class updates `current_location` as appropriate.
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*/
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class IREmitter : public IR::IREmitter {
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public:
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2018-02-11 22:53:46 +00:00
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explicit IREmitter(IR::Block& block) : IR::IREmitter(block) {}
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2018-01-12 19:34:25 +00:00
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explicit IREmitter(IR::Block& block, LocationDescriptor descriptor) : IR::IREmitter(block), current_location(descriptor) {}
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2018-01-06 21:15:25 +00:00
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2018-02-11 22:53:46 +00:00
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boost::optional<LocationDescriptor> current_location;
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2018-01-06 21:15:25 +00:00
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u64 PC();
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u64 AlignPC(size_t alignment);
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2018-01-07 16:33:02 +00:00
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void SetCheckBit(const IR::U1& value);
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2018-01-07 11:31:20 +00:00
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IR::U1 GetCFlag();
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void SetNZCV(const IR::NZCV& nzcv);
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2018-01-08 22:03:03 +00:00
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void CallSupervisor(u32 imm);
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2018-01-13 17:54:29 +00:00
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void ExceptionRaised(Exception exception);
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2018-02-11 22:53:46 +00:00
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void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value);
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2018-02-11 23:27:28 +00:00
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void DataSynchronizationBarrier();
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void DataMemoryBarrier();
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2018-02-20 16:54:10 +00:00
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IR::U64 GetCNTPCT(); // TODO: Ensure sub-basic-block cycle counts are updated before this.
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2018-02-20 16:44:13 +00:00
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IR::U32 GetCTR();
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2018-02-12 00:06:44 +00:00
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IR::U32 GetDCZID();
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IR::U64 GetTPIDRRO();
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2018-01-08 22:03:03 +00:00
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
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void ClearExclusive();
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void SetExclusive(const IR::U64& vaddr, size_t byte_size);
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2018-01-10 01:13:23 +00:00
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IR::U8 ReadMemory8(const IR::U64& vaddr);
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IR::U16 ReadMemory16(const IR::U64& vaddr);
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IR::U32 ReadMemory32(const IR::U64& vaddr);
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IR::U64 ReadMemory64(const IR::U64& vaddr);
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2018-01-24 15:55:59 +00:00
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IR::U128 ReadMemory128(const IR::U64& vaddr);
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2018-01-10 01:13:23 +00:00
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void WriteMemory8(const IR::U64& vaddr, const IR::U8& value);
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void WriteMemory16(const IR::U64& vaddr, const IR::U16& value);
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void WriteMemory32(const IR::U64& vaddr, const IR::U32& value);
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void WriteMemory64(const IR::U64& vaddr, const IR::U64& value);
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2018-01-24 15:55:59 +00:00
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void WriteMemory128(const IR::U64& vaddr, const IR::U128& value);
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
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IR::U32 ExclusiveWriteMemory8(const IR::U64& vaddr, const IR::U8& value);
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IR::U32 ExclusiveWriteMemory16(const IR::U64& vaddr, const IR::U16& value);
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IR::U32 ExclusiveWriteMemory32(const IR::U64& vaddr, const IR::U32& value);
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IR::U32 ExclusiveWriteMemory64(const IR::U64& vaddr, const IR::U64& value);
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IR::U32 ExclusiveWriteMemory128(const IR::U64& vaddr, const IR::U128& value);
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2018-01-10 01:13:23 +00:00
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2018-01-06 21:15:25 +00:00
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IR::U32 GetW(Reg source_reg);
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IR::U64 GetX(Reg source_reg);
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2018-01-26 18:35:19 +00:00
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IR::U128 GetS(Vec source_vec);
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2018-01-21 17:45:43 +00:00
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IR::U128 GetD(Vec source_vec);
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IR::U128 GetQ(Vec source_vec);
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2018-01-07 11:31:20 +00:00
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IR::U64 GetSP();
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2018-01-06 21:15:25 +00:00
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void SetW(Reg dest_reg, const IR::U32& value);
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void SetX(Reg dest_reg, const IR::U64& value);
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2018-01-26 18:35:19 +00:00
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void SetS(Vec dest_vec, const IR::U128& value);
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2018-01-21 17:45:43 +00:00
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void SetD(Vec dest_vec, const IR::U128& value);
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void SetQ(Vec dest_vec, const IR::U128& value);
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2018-01-07 11:31:20 +00:00
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void SetSP(const IR::U64& value);
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2018-01-07 13:56:32 +00:00
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void SetPC(const IR::U64& value);
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2018-01-06 21:15:25 +00:00
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};
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2018-01-26 13:51:48 +00:00
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} // namespace Dynarmic::A64
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