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A64: Implement SADDW/SADDW2

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Lioncash 2018-04-02 20:10:22 -04:00 committed by MerryMage
parent 78a047f0f9
commit 00af6eeab9
3 changed files with 18 additions and 2 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -676,7 +676,7 @@ INST(NOT, "NOT", "0Q101
// Data Processing - FP and SIMD - SIMD three different // Data Processing - FP and SIMD - SIMD three different
//INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd") //INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd")
//INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd") INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd")
//INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd") //INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd")
//INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd") //INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd")
//INST(ADDHN, "ADDHN, ADDHN2", "0Q001110zz1mmmmm010000nnnnnddddd") //INST(ADDHN, "ADDHN, ADDHN2", "0Q001110zz1mmmmm010000nnnnnddddd")

2
src/frontend/A64/translate/impl/impl.h
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@ -803,7 +803,7 @@ struct TranslatorVisitor final {
// Data Processing - FP and SIMD - SIMD three different // Data Processing - FP and SIMD - SIMD three different
bool SADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool SADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
bool SADDW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); bool SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
bool SSUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool SSUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
bool SSUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); bool SSUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
bool ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); bool ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);

16
src/frontend/A64/translate/impl/simd_three_different.cpp
View file

@ -8,6 +8,22 @@
namespace Dynarmic::A64 { namespace Dynarmic::A64 {
bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t part = Q ? 1 : 0;
const IR::U128 operand1 = V(128, Vn);
const IR::U128 operand2 = ir.VectorSignExtend(esize, Vpart(64, Vm, part));
const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2);
V(128, Vd, result);
return true;
}
bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) { if (size == 0b11) {
return ReservedValue(); return ReservedValue();