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asimd: Prevent misdecodes from occurring

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Pointed out by Mary when reviewing the shift code.
This commit is contained in:
Lioncash 2020-06-18 14:59:32 -04:00
parent 6ca20c2fe3
commit 00b2f9b319
2 changed files with 14 additions and 3 deletions
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10
src/frontend/A32/decoder/asimd.h
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@ -8,6 +8,7 @@
#include <algorithm> #include <algorithm>
#include <functional> #include <functional>
#include <optional> #include <optional>
#include <set>
#include <vector> #include <vector>
#include "common/bit_util.h" #include "common/bit_util.h"
@ -35,6 +36,15 @@ std::vector<ASIMDMatcher<V>> GetASIMDDecodeTable() {
return Common::BitCount(matcher1.GetMask()) > Common::BitCount(matcher2.GetMask()); return Common::BitCount(matcher1.GetMask()) > Common::BitCount(matcher2.GetMask());
}); });
// Exceptions to the above rule of thumb.
const std::set<std::string> comes_first{
"VBIC, VMOV, VMVN, VORR (immediate)"
};
std::stable_partition(table.begin(), table.end(), [&](const auto& matcher) {
return comes_first.count(matcher.GetName()) > 0;
});
return table; return table;
} }

7
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
View file

@ -3,6 +3,7 @@
* SPDX-License-Identifier: 0BSD * SPDX-License-Identifier: 0BSD
*/ */
#include "common/assert.h"
#include "common/bit_util.h" #include "common/bit_util.h"
#include "frontend/A32/translate/impl/translate_arm.h" #include "frontend/A32/translate/impl/translate_arm.h"
@ -53,7 +54,7 @@ bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd,
// Technically just a related encoding (One register and modified immediate instructions) // Technically just a related encoding (One register and modified immediate instructions)
if (!L && Common::Bits<3, 5>(imm6) == 0) { if (!L && Common::Bits<3, 5>(imm6) == 0) {
return v.UndefinedInstruction(); ASSERT_FALSE();
} }
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6); const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6);
@ -106,7 +107,7 @@ bool ArmTranslatorVisitor::asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bo
// Technically just a related encoding (One register and modified immediate instructions) // Technically just a related encoding (One register and modified immediate instructions)
if (!L && Common::Bits<3, 5>(imm6) == 0) { if (!L && Common::Bits<3, 5>(imm6) == 0) {
return UndefinedInstruction(); ASSERT_FALSE();
} }
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6); const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6);
@ -160,7 +161,7 @@ bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bo
// Technically just a related encoding (One register and modified immediate instructions) // Technically just a related encoding (One register and modified immediate instructions)
if (!L && Common::Bits<3, 5>(imm6) == 0) { if (!L && Common::Bits<3, 5>(imm6) == 0) {
return UndefinedInstruction(); ASSERT_FALSE();
} }
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, L, imm6); const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, L, imm6);