mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

emit_arm64_a32: Implement A32GetCpsr

Browse source
This commit is contained in:
Merry 2022-07-26 16:31:24 +01:00 committed by merry
parent 8a0359ec52
commit 0b53290dd7
2 changed files with 29 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/dynarmic/backend/arm64/a32_jitstate.h
View file

@ -15,17 +15,17 @@
namespace Dynarmic::Backend::Arm64 { namespace Dynarmic::Backend::Arm64 {
struct A32JitState { struct A32JitState {
u32 cpsr_nzcv = 0;
u32 cpsr_ge = 0;
u32 cpsr_jaifm = 0;
u32 cpsr_q = 0;
std::array<u32, 16> regs{}; std::array<u32, 16> regs{};
u32 upper_location_descriptor; u32 upper_location_descriptor;
alignas(16) std::array<u32, 64> ext_regs{}; alignas(16) std::array<u32, 64> ext_regs{};
u32 cpsr_nzcv = 0;
u32 cpsr_ge = 0;
u32 cpsr_jaifm = 0;
u32 cpsr_q = 0;
u32 fpsr = 0; u32 fpsr = 0;
u32 exclusive_state = 0; u32 exclusive_state = 0;

28
src/dynarmic/backend/arm64/emit_arm64_a32.cpp
View file

@ -221,10 +221,30 @@ void EmitIR<IR::Opcode::A32SetVector>(oaknut::CodeGenerator& code, EmitContext&
template<> template<>
void EmitIR<IR::Opcode::A32GetCpsr>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::A32GetCpsr>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto Wcpsr = ctx.reg_alloc.WriteW(inst);
(void)ctx; RegAlloc::Realize(Wcpsr);
(void)inst;
ASSERT_FALSE("Unimplemented"); static_assert(offsetof(A32JitState, cpsr_jaifm) + sizeof(u32) == offsetof(A32JitState, cpsr_q));
code.LDR(Wcpsr, Xstate, offsetof(A32JitState, cpsr_nzcv));
code.LDP(Wscratch0, Wscratch1, Xstate, offsetof(A32JitState, cpsr_jaifm));
code.ORR(Wcpsr, Wcpsr, Wscratch0);
code.ORR(Wcpsr, Wcpsr, Wscratch1);
code.LDR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_ge));
code.AND(Wscratch0, Wscratch0, 0x80808080);
code.MOV(Wscratch1, 0x00204081);
code.MUL(Wscratch0, Wscratch0, Wscratch1);
code.AND(Wscratch0, Wscratch0, 0xf0000000);
code.ORR(Wcpsr, Wcpsr, Wscratch0, LSR, 12);
code.LDR(Wscratch0, Xstate, offsetof(A32JitState, upper_location_descriptor));
code.AND(Wscratch0, Wscratch0, 0b11);
// 9 8 7 6 5
// E T
code.ORR(Wscratch0, Wscratch0, Wscratch0, LSL, 3);
code.AND(Wscratch0, Wscratch0, 0x11111111);
code.ORR(Wcpsr, Wcpsr, Wscratch0, LSL, 5);
} }
template<> template<>