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A64: Implement FMSUB

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This commit is contained in:
MerryMage 2018-04-04 19:00:28 +01:00
parent 69e00d225c
commit 0d83032a6f
2 changed files with 15 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -940,6 +940,6 @@ INST(FCSEL_float, "FCSEL", "00011
// Data Processing - FP and SIMD - Floating point data processing three register
INST(FMADD_float, "FMADD", "00011111yy0mmmmm0aaaaannnnnddddd")
//INST(FMSUB_float, "FMSUB", "00011111yy0mmmmm1aaaaannnnnddddd")
INST(FMSUB_float, "FMSUB", "00011111yy0mmmmm1aaaaannnnnddddd")
//INST(FNMADD_float, "FNMADD", "00011111yy1mmmmm0aaaaannnnnddddd")
//INST(FNMSUB_float, "FNMSUB", "00011111yy1mmmmm1aaaaannnnnddddd")

14
src/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp
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@ -37,4 +37,18 @@ bool TranslatorVisitor::FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd)
return true;
}
bool TranslatorVisitor::FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
const auto datasize = GetDataSize(type);
if (!datasize || *datasize == 16) {
return UnallocatedEncoding();
}
const IR::U32U64 operanda = V_scalar(*datasize, Va);
const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
const IR::U32U64 result = ir.FPMulAdd(operanda, ir.FPNeg(operand1), operand2, true);
V_scalar(*datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64