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A64: Implement FRECPS, vector/scalar single/double variants

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This commit is contained in:
MerryMage 2018-07-25 19:11:43 +01:00
parent 901bd9b4e2
commit 10de36394e
3 changed files with 27 additions and 2 deletions
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4
src/frontend/A64/decoder/a64.inc
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@ -343,7 +343,7 @@ INST(DUP_elt_1, "DUP (element)", "01011
//INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd") //INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd")
INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd") INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd")
//INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd") //INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd")
//INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd") INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd")
//INST(FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd") //INST(FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd")
INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd") INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd")
//INST(FCMGE_reg_1, "FCMGE (register)", "01111110010mmmmm001001nnnnnddddd") //INST(FCMGE_reg_1, "FCMGE (register)", "01111110010mmmmm001001nnnnnddddd")
@ -731,7 +731,7 @@ INST(FADD_2, "FADD (vector)", "0Q001
//INST(FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd") //INST(FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd")
INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd") INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd")
//INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd") //INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd")
//INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd") INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd")
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd") INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")
INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd") INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
//INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd") //INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd")

11
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -181,6 +181,17 @@ bool TranslatorVisitor::FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::FRECPS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32;
const IR::U32U64 operand1 = V_scalar(esize, Vn);
const IR::U32U64 operand2 = V_scalar(esize, Vm);
const IR::U32U64 result = ir.FPRecipStepFused(operand1, operand2);
V_scalar(esize, Vd, result);
return true;
}
bool TranslatorVisitor::FRSQRTS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::FRSQRTS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32; const size_t esize = sz ? 64 : 32;

14
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -622,6 +622,20 @@ bool TranslatorVisitor::FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::FRECPS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
const size_t esize = sz ? 64 : 32;
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.FPVectorRecipStepFused(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
if (sz && !Q) { if (sz && !Q) {
return ReservedValue(); return ReservedValue();